Having already introduced various extensions and modifications of the ADRC structure and its discrete-time variants for software-based implementation, we are ready to put it to work! To show how ADRC performs in actual applications, here we consider two laboratory testbeds representative of a spectrum of real control problems one can encounter in engineering practice. For those application examples, custom-made ADRC-based solutions are devised, designed, and deployed. We make an arbitrary choice to use the previously derived discrete-time state-space ADRC in the first example and its transfer function form for the implementation in the second example. For each of the considered cases, we will show similar steps including a brief plant description, formulation of the control problem, implementation and commissioning of the selected ADRC (based on already introduced “cooking recipes”), initial validation in simulation, and finally physical validation on target hardware. The examples will differ vastly regarding not only their dynamics but also the method chosen for plant modeling, covering both an experimentally driven approach and a case based on theoretical and numerical analyses.
11.1 Heater Temperature Control
A temperature controller is often used in scenarios where an object is required to be heated, cooled, or both, to remain at the target temperature, regardless of the changing environment around it. Many industrial processes require a precisely kept temperature to ensure product quality, prevent equipment damage, improve efficiency, and maintain a safe working environment. In this example, we utilize Temperature Control Lab (TCLab), which is a low-cost and commercially available Arduino-based education module. 1 It emulates a real, multi-input multi-output process control plant, where two transistors (working as heaters) and two thermistor temperature sensors serve as the plant’s inputs and outputs, respectively. The usually considered control objective in TCLab is to apply power to the heaters to keep desired temperatures. The two heater units are deliberately placed by the designers on the printed circuit board in close proximity to each other to allow heat transfer by convection and thermal radiation. This makes the control of TCLab additionally challenging as the operation of one heater influences the other, and vice versa, thus creating a cross-coupling effect. At the same time, some of the heat is also transferred away from the device to the surroundings. In our case, we will be considering TCLab as an SISO control problem, where the control objective is to govern the temperature of the first heater, and the influence of the second heater is treated as an unmodeled, external disturbance to the first one.
The input signals to the TCLab are normalized values of 0 %…100 %, corresponding to 0 W…10 W, which is the PWM-controlled power range of the heaters. The output signals are expressed, for user’s convenience, in degree Celsius but originate from analog voltages of the temperature sensors captured using analog-to-digital converters. Their accuracy is ± 1∘C at best. A USB cable connects the Arduino to a computer allowing serial data communication. An overview of the TCLab device setup can be seen in Fig. 11.1.
Fig. 11.1
Target hardware for the temperature control example: TCLab board, available from APMonitor, to be attached to an Arduino development board
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Plant Modeling
Although the ADRC structure has been shown in Chap. 5 to have a considerable level of robustness against parametric and structural uncertainties and external disturbances, the procedure of system mathematical modeling should not be deemed unnecessary and upfront discarded. The benefit of even a rough plant modeling for the purpose of ADRC design was shown before in Sect. 6.1. Therefore, for the TCLab, we will follow the straightforward modeling procedure from Sect. 5.1 of experimentally capturing the system’s core behavior using its step response. To avoid confusion, Table 11.1 contains the established terminology and notation.
Table 11.1
Notation used in the TCLab example with real components seen also in Fig. 11.1
Element
Assigned role
Symbol
Heater 1
Control input
u
Temperature sensor 1
Controlled variable
y
Temperature sensor 1 (model)
Controlled variable
ym
Heater 2
Disturbance input
ud
Temperature sensor 2
Disturbance output
yd
To get the step response of TCLab, we use a stepwise change in the input signal u(t) = 40 % ⋅ σ(t) at time t = 300 s. The sampling interval is set to Ts = 3 s. The results of such an open-loop test are presented in Fig. 11.2. One can notice that the process exhibits mostly first-order low-pass behavior, similar to the one discussed in Sect. 5.1, with an approximate dominant time constant T ≈ 182 s and gain \(K \approx 0.58\,\frac {{ }^{\circ }\mathrm {C}}{\% _{\mathrm {Heater}}}\). In this case, the process also has a dead time of Td ≈ 18 s. Therefore, based on the collected data, the rough plant model of the TCLab is chosen as
$$\displaystyle \begin{aligned} T \cdot \frac{\mathrm{d}y_{\mathrm{m}}(t)}{\mathrm{d}t} = - y_{\mathrm{m}}(t) + K \cdot u(t - T_{\mathrm{d}}) \end{aligned}$$
Fig. 11.2
Open-loop step responses of TCLab (left figure, showing the effects of both control and disturbance inputs), leading to the model (11.1). Plant and model are compared in the center figure. Note that the model output is shifted by the ambient temperature for comparability. To make the dead time more visible, a zoomed-in detail of the model comparison is repeated in the right figure
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or alternatively in a transfer function form, similar to (9.5):
To assess the level of model fitting, the step response of (11.1), denoted as ym(t), to the same stepwise input signal u(t) is added to Fig. 11.2. It should be that (11.1) is a rough description of the actual system, not including phenomena like sensor noise or cross-coupling from the other heater, which we use as a disturbance input. We could follow the path of more accurate modeling but that would require investment of additional resources, like time, measurement capabilities, etc. Instead, we will deliberately use the simple SISO model (11.1) to show that ADRC can effectively work even if only limited information about the controlled system is available.
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ADRC Design
To develop an ADRC scheme for the considered TCLab system, let us make use of the already possessed knowledge and follow the “cooking recipe” for the discrete-time state-space form of linear ADRC given on page 130:
1.
Plant modeling: The plant order of P(s) in (11.1) is N = 1, calling for a first-order ADRC. From the step response, we already obtained plant parameter estimations, namely \(K \approx 0.58\,\frac {{ }^{\circ }\mathrm {C}}{\%_{\mathrm {Heater}}}\), T ≈ 182 s, and Td ≈ 18 s. Recalling Table 3.1, we therefore determine the critical gain parameter as \(b_0 = \frac {K}{T} \approx 0.003\,\frac {{ }^{\circ }\mathrm {C}}{\%_{\mathrm {Heater}} \cdot \mathrm {s}}\).
2.
Controller and observer tuning: We are not given certain design goals and therefore use a settling time Tsettle,98% ≈ 300 s to be at least somewhat faster than the open-loop step response. With (3.21) we calculate ωCL ≈ 0.013 rad∕s. This allows for a practically acceptable signal-to-noise ratio. The controller gain k1 is then computed using the general design equation for bandwidth parameterization given by (8.13), or through referring to Table A.5.1, which results in k1 ≈ 0.0128. Given the noise levels in the open-loop measurements collected so far, we select the relative observer bandwidth factor to a conservative value of kESO = 3. To compute the observer gains, we put ωCL and kESO into the general design Eq. (8.6), or once more refer to Table A.5.1, obtaining l1 ≈ 0.2094 and l2 ≈ 0.0041.
3.
Implementation: In our model-based implementation, we use the discrete-time state-space form of ADRC for plants with dead time, depicted in Fig. 9.9. It requires the discrete-time control law (8.1) and the discrete-time ESO equation (9.6) to be implemented. Since we roughly know the TCLab dead time to be Td ≈ 18 s, the observer synchronization method from Sect. 9.4 is applied with the control signal being delayed by \(n_{\mathrm {d}} = 6 \approx \frac {T_{\mathrm {d}}}{T_{\mathrm {s}}}\) samples. The sampling interval used for the discrete implementation is Ts = 3 s.
4.
Customization: Our practical controller is extended by a discrete-time magnitude and rate limitation add-on block from Sect. 9.1. Output limits umin = 0 %, umax = 100 % follow from TCLab’s normalized heater power range. The rate limitation is, primarily for demonstration purposes, configured with values \( \Delta u_{\mathrm {min/max}} = \pm 1\,\frac {\%}{\mathrm {s}}\). Finally, since the TCLab starts its operation at room temperature (most likely not zero), we apply the direct initialization from Sect. 9.2 and use an initial ambient temperature measurement as a starting condition to bumplessly switch on both observer and controller.
Given the above design, the ADRC scheme for the TCLab can be represented with a block diagram seen in Fig. 11.3.
Fig. 11.3
Discrete-time ADRC for TCLab, state-space implementation, enhanced by a control signal limitation block and delayed control signal to synchronize the observer with the time-delayed plant. Note that we, in this example, denote the limited controller output simply as u
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Validation in Simulation
Before we deploy the above ADRC on the actual TCLab, we will first test it in simulation, which is overall a good practice in control engineering that helps with concept validation and code debugging. Here, the control objective is simply to keep the reference temperature of the first heater by manipulating its input power. We can only test here an SISO control system since the influence of the second heater was assumed to be a disturbance; hence we do not have a model for it. The presence of dead time in the TCLab system is an excellent opportunity to apply the ESO dead time synchronization method described in Sect. 9.4. Therefore, we test two ADRC designs, one with synchronization turned on (denoted as “sync. ON”) and the other without synchronization (“sync. OFF”). The test consists of a stepwise change of the reference signal r(t) to 40∘C at time t = 0 s, starting from a simulated ambient temperature of 23∘C. The results in Fig. 11.4 show the closed-loop behavior, with y(t) approaching r(t). It is nicely evident that if information about the dead time is available, it can be put to good use, leading to reduced efforts and oscillations in the controller output signal.
Fig. 11.4
Simulation validation of the closed-loop step response using discrete-time ADRC. Even though similar regulation performance can be seen for the controlled variable y of the two tested designs, ADRC without dead time synchronization in the ESO (“sync. OFF”) generates a visibly larger and more oscillatory control signal u than the scenario with synchronization turned on (“sync. ON”), which is not desirable, e.g., from an energy usage point of view
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Validation in Experiment
Since our initial control concept for the TCLab temperature control was successfully tested in a simulated environment, we can now feel more comfortable deploying it on the real device. The discretized ADRC algorithm is implemented on the Arduino board of the TCLab. The software implementation of the “cooking recipe” is a straightforward procedure as it is shown in Sect. 10.2.1, extended by the delay synchronization. This time, the control objective is to keep the reference temperature of the first heater by manipulating its input power while remaining insensitive against the interferences from the second heater, which acts as an unmodeled, external disturbance. Similar to the simulation validation, we are interested here in how the dead time synchronization method from Sect. 9.4 works on the control performance; hence we test again the two cases “sync. ON” and “sync. OFF.” As for the details of the test itself, at time t = 0 s, a stepwise change of the reference signal r(t) to 40∘C occurs followed by a stepwise change at t = 1200 s of the disturbance input signal ud(t) to 80 %. From the results in Fig. 11.5, one can see that the control objective is being realized in a practically acceptable manner with the output y(t) exhibiting robustness to the influence of the second heater, which is especially visible in the disturbance countering measures by the control signal u(t).
Fig. 11.5
Experimental validation of the closed-loop step response and disturbance rejection using discrete-time ADRC (without and with dead time synchronization). A user-defined disturbance from the second heater ud(t) = 80 % becomes effective starting from t = 1200 s. In contrast to the open-loop case in Fig. 11.2, the effect of the disturbance is now being compensated very well by the controller, as visible in the controller outputs
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11.2 DC-DC Converter Voltage Control
Let us now dive into an application domain with significantly smaller time constants: power electronics. More specifically, the problem of output voltage control in a step-down (buck) DC-DC converter shall be addressed. Once more, we consciously decided to target an affordable, scaled-down experimental platform. This shall encourage readers to replicate these results and lower the barriers to getting started with own experiments of ADRC in a real-world control loop. Our experimental setup consists of a development board with a 32-bit microcontroller unit (MCU) attached to a second board with the DC-DC converter and a switchable load resistor, as shown in Fig. 11.6. Both are available commercially. 2
Fig. 11.6
Target hardware for the voltage control example: DC-DC converter board attached to a microcontroller development board, both available from Texas Instruments
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This second application example once more aims to implement an ADRC control loop using the tools introduced in this book. The tuning parameters achieved may then serve as a solid starting point to fine-tune the loop with respect to certain control-related optimization criteria, but this is not our goal. Instead, we intend to emphasize the fact that a working implementation of ADRC can be found without trial and error, by following the guidelines presented in previous chapters.
Plant Modeling
The converter shall be operated in the so-called voltage mode, i.e., a single control loop regulating the output voltage. Control signal will be the duty cycle, i.e., the relative on-time of the converter’s high-side switch. For the intended ADRC design, we therefore must determine a model with input duty cycle and output output voltage.
A simplified schematic of the step-down (buck) DC-DC converter is shown in Fig. 11.7. Compared to a “textbook” converter, mixed-type output capacitors are being used here: higher capacitance electrolytic capacitors with large equivalent series resistance (ESR) combined with low-capacitance low-ESR ceramic capacitors. As pointed out in dedicated literature, this can considerably complicate the process of modeling and control of the plant. 3
Fig. 11.7
Simplified schematic of the synchronous buck DC-DC converter. Inductor ESR and current sense resistor have been combined (rL + rCS)
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In frequency domain, a model for the output voltage control task can be derived from the voltage divider formed by the load and the power stage components:
Analytically, this would result in a relatively convoluted transfer function. Remembering that, apart from the plant order N, ADRC requires only one plant model parameter b0, we do not need to be afraid, however. With the component values listed in Table 11.2, Bode diagrams of the plant dynamics can be computed numerically for the base and full load cases. As shown in Fig. 11.8, one can extract the required information easily from these diagrams. In a frequency interval relevant to our control design (aiming for bandwidth in the kilohertz range), dynamics are clearly of order N = 2. Using the frequency-domain method introduced in Sect. 5.1.2, an approximate value of b0 can be obtained with \(b_0 \approx 150000^2 {\frac {\text{V}}{\text{s}^2}}\). This already concludes our efforts regarding plant modeling of this converter.
Fig. 11.8
Bode diagrams of the plant dynamics for the two possible cases (base load and full load). As expected, the differences are negligible. In the frequency range relevant to the control of this plant, the dynamics predominantly exhibit second-order behavior. Using the approach introduced in Sect. 5.1.2, we can find the plant models’ critical gain parameter b0 from the crossover frequency of a straight-line approximation of the magnitude plot
Table 11.2
Component values used for creating the plant model of the DC-DC converter
Description and symbol
Value
Description and symbol
Value
Capacitance C1
330 μF
ESR rC1
150 m Ω
Capacitance C2
66 μF
ESR rC2
2 m Ω
Inductance L
4.8 μH
ESR rL + rCS (current sense)
40 m Ω
Load resistance RLoad (base load)
7.5 Ω
Load resistance RLoad (full load)
1.6 Ω
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ADRC Design
The switching frequency of the DC-DC converter is 200 kHz. Updating the control loop every switching period will allow us to aim for a large closed-loop bandwidth but require a computationally efficient implementation. We will therefore use the low-footprint dual-feedback transfer function form of ADRC described in Sect. 8.3 and follow the “cooking recipe” from page 138.
1.
Plant modeling: As depicted in Fig. 11.8, the plant is of order N = 2, with an approximate critical gain parameter value of b0 = 1500002 = 22.5 ⋅ 109.
2.
Controller and observer tuning: Aiming for a 98 % settling time of Tsettle = 200 μs leads, when put into (3.21), to a desired closed-loop bandwidth ωCL = 29000 rad∕s. To minimize the effects of measurement noise, the observer bandwidth will be chosen conservatively with kESO = 3. Furthermore, we will make use of half-gain tuning for the observer as described in Sect. 9.3.
3.
Implementation: As already mentioned, the minimum-footprint transfer function variant shown in Fig. 8.9 will be used, with a sampling interval \(T_{\mathrm {s}} = \frac {1}{200\,\mathrm {kHz}} = 5\,{\mu s}\).
4.
Customization: A magnitude limitation of the controller output to the possible interval of the PWM duty cycle [0 %, 100 %] is added, i.e., umin = 0 and umax = 1.
Figure 11.9 gives an overview of the control loop in block diagram form. The controller will be implemented on the microcontroller shown in Fig. 11.6.
Fig. 11.9
Discrete-time ADRC for the DC-DC converter. The dual-feedback transfer function implementation is being used, enhanced by a control signal limitation block. In this example, we also denote the limited controller output simply as u
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Validation in Simulation
A simulation model of the converter as depicted in Fig. 11.7 using the parameter values from Table 11.2 was set up to analyze the closed-loop behavior for the output voltage control task. A small simulation scenario was designed, consisting of the following elements, which are executed after the output voltage is settled at r = 2 V:
A step of the reference signal r to a new desired output voltage value 2.2 V occurring at t = 2 ms
A load step at t = 4 ms (activating full load on the converter board)
A load dump at t = 6 ms (reduction to the base load resistor)
Figure 11.10 shows the simulation results. To examine the controller’s sensitivity to measurement noise, a Gaussian noise signal was added to the output voltage with σ = 2 mV. While not exactly achieving a settling time of 200 μs in the transient after the reference step, these results obtained by only following the “cooking recipe” without further tweaking are already very well usable. While the performance could, as always, still be refined if necessary, we will therefore now directly transfer this design into practice.
Fig. 11.10
Simulation results of DC-DC converter voltage control using second-order discrete-time ADRC. At time t = 2 ms, a reference signal step from 2 V to 2.2 V occurs. Between t = 4 ms and t = 6 ms, the converter operates in its full load condition
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Validation in Experiment
The controller implementation on the MCU target platform was carried out in the C programming language. For selected ADRC form, this was done as described in detail in Sect. 10.2.2, but for the second-order case and—owing to the properties of the MCU target platform—only using single-precision floating point numbers. The implementation made use of the high-resolution PWM capabilities of the selected MCU and, at a switching frequency of 200 kHz, used a PWM dead-band of approximately 60 μs.
Measurement results are presented in Fig. 11.11. They were recorded in a buffer on the MCU and later transferred to a host PC, thereby revealing the exact values as measured and computed by the MCU. The virtually identical reference step transient confirms that the design was successfully transferred to the target platform.
Fig. 11.11
Measurement results from the DC-DC converter target hardware, when running through the same test scenario (reference signal step, load step, and load dump). Overall, a very good replication of the simulation data was achieved. Settling time and required control efforts following the disturbance steps are (if only slightly) higher than in simulation. The reference signal step transient is almost indistinguishable from its counterpart in Fig. 11.10
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Summarizing the DC-DC converter example, we can state that a controller design which can serve as a very solid starting point for further optimization could directly be obtained by following the “cooking recipe” and using the tools provided here. Exactly that was our intention when writing this book: providing a direct path from principles to practice.
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