10. Approximate High-Level Synthesis of Custom Hardware

Approximate computing exploits trade-offs between quality and energy/performance of computed results for inherently error-tolerant applications. At the hardware level, various components, such as arithmetic and logic units (ALUs), have been proposed to build approximate hardware processors. However, existing work has been mostly ad hoc or using expensive iterative simulation and resynthesis for design space exploration. In this chapter, we present an approximate high-level synthesis (AHLS) approach that utilizes approximate operators in synthesizing an energy- or performance-optimized register-transfer level (RTL) design from its high-level C description under overall quality constraints at design outputs. In effective AHLS, fast and accurate quality and energy models are required together with an optimization technique to efficiently find a Pareto-optimal design. Quality effects of hardware approximations strongly depend on input data. In this work, a statistical formulation is employed to capture input dependency and analytically estimate quality using one-time profiling only. Energy and performance savings due to approximations strongly depend on operation scheduling and binding. We present an approach that estimates the performance, voltage scaling, and energy impact of approximations while taking into account tight interactions with existing synthesis tasks. Quality, performance, and energy estimation methods are further combined with novel AHLS-specific loop optimizations and heuristic solvers that find Pareto-optimized solutions in an efficient manner. Results show that our tool can achieve near-optimal results with low runtimes, demonstrating energy savings of, on average, more than 77.6%, where up to 24.5% higher savings are achieved compared to approaches that only consider switching activity.