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Erschienen in:
2011 | OriginalPaper | Buchkapitel
Architecture Extensions for Efficient Management of Scratch-Pad Memory
verfasst von : José V. Busquets-Mataix, Carlos Catalá, Antonio Martí-Campoy
Erschienen in: Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation
Verlag: Springer Berlin Heidelberg
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Nowadays, many embedded processors include in their architecture on-chip static memories, so called scratch-pad memories (SPM). Compared to cache, these memories do not require complex control logic, thus resulting in increased efficiency both in silicon area and energy consumption. Last years, many papers have proposed algorithms to allocate memory segments in SPM in order to enhance its usage. However, very few care about the SPM architecture itself, to make it more controllable, more power efficient and faster. This paper proposes architecture extensions to automatically load code into the SPM whilst it is fetched for execution to reduce the SPM updating delays, which motivates a very dynamic use of the SPM. We test our proposal in a derivation of the Simplescalar simulator, with typical embedded benchmarks. The results show improvements, on average, of 30.6% in energy saving and 7.6% in performance compared to a system with cache.