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Microelectronic packaging has been recognized as an important "enabler" for the solid­ state revolution in electronics which we have witnessed in the last third of the twentieth century. Packaging has provided the necessary external wiring and interconnection capability for transistors and integrated circuits while they have gone through their own spectacular revolution from discrete device to gigascale integration. At IBM we are proud to have created the initial, simple concept of flip chip with solder bump connections at a time when a better way was needed to boost the reliability and improve the manufacturability of semiconductors. The basic design which was chosen for SLT (Solid Logic Technology) in the 1960s was easily extended to integrated circuits in the '70s and VLSI in the '80s and '90s. Three I/O bumps have grown to 3000 with even more anticipated for the future. The package families have evolved from thick-film (SLT) to thin-film (metallized ceramic) to co-fired multi-layer ceramic. A later family or ceramics with matching expansivity to sili­ con and copper internal wiring was developed as a predecessor of the chip interconnection revolution in copper, multilevel, submicron wiring. Powerful server packages have been de­ veloped in which the combined chip and package copper wiring exceeds a kilometer. All of this was achieved with the constant objective of minimizing circuit delays through short, efficient interconnects.



History of Flip Chip and Area Array Technology

Chapter 1. History of Flip Chip and Area Array Technology

The concept of interconnecting a chip to a package in a face-down or “flip chip” orientation is simple enough, and forty years old. The idea of having input-output connections all over the face of a flip chip is also a simple idea, and twenty-five years old. Then, how is it, in the last days of the twentieth century, that the electronics industry finds itself in the midst of a revolution in electronic assembly referred to as flip-chip area-array packaging?
Paul A. Totta

Chip-Level Technology


2. Wafer Bumping

Assuming that the “paradigm shift” in chip joining from peripheral wiring to area-array flip-chip technology is strategic for future electronics, there are immediate questions which emerge: Who will put bumps on chips and how? Will the same bumped chips be joined to both ceramic and organic packages? Must all chips be joined with high-melting or low-melting solders, or not with solder at all, but with conductive adhesives? This chapter will illustrate that there is presently great diversity in flip chip design and joining. There are reasonable arguments for doing essentially the same job in many different ways. You will find process and structure descriptions from numerous champions of the most prominent alternatives in chip joining without judgements or critiques as to what is good or bad. The marketplace is expected to be the ultimate sorting place which will accept some of the best, and reject others which fall short due to cost, manufacturability, reliability or functionality.
Paul Totta, Glenn Rinne, Peter Elenius, Michael Varnau, Thomas Oppert, Elke Zakel, Don Hayes, David Wallace, Helge Kristiansen, Johan Liu

3. Wafer-Level Test

Successful development and manufacture of semiconductor components is highly dependent on test verification at several critical steps throughout the process and at multiple levels of packaging. An effective test methodology spans a broad range of products, diverse test systems and product-handling equipment, and encompasses several test techniques. A reliable and cost-effective product contacting method is a key requirement for all of these test techniques to be successful.
Gobinda Das, Franco Motika, Eugene Atwood

4. Known Good Die (KGD)

A Known Good Die (KGD) is defined as “a package type fully supported by suppliers to meet or exceed quality, reliability, and functional data sheet specifications, with non-standardized (die specific) but completely and electronically transferable mechanical specifications”. In other words, the category of challenges associated with KGD are no different than those faced by any customer using a new or different package type. Electrical performance and power dissipation values and variations, mechanical specifications, handling issues, cooling, attachment to the next level of assembly, etc., all must be reevaluated and solutions found whenever the package changes, even though the die remains identical. Hence, KGD is no more than a different package type for a known die that incorporates mechanical specifications that cannot be standardized (unless or until die designers agree on standard die sizes and pad layouts, etc.). The challenges associated with KGD usage may be greater than with standardized packaged dice because of less standardization of mechanical specifications, handling of bare dice, etc. The ben-efits, challenges, and approaches to KGD usage are discussed in this chapter.
Claude L. Bertin, Lo-Soun Su, Jody Van Horn

5. Wafer Finishing—Dicing,Picking,Shipping

Progress in die separation technology or “dicing” has improved device yield and productivity over the years. Today, the basic dicing process is one in which a rotating, abrasive-edged blade is positioned to cut in the “streets” or the “kerf” spaces between functional integrated circuits or other devices. The thin, 25 µm cutting blade rotates at very high speeds (30,000 to 60,000 rpm with blade-edge linear speeds of 83 to 175 m/sec). Dicing equipment has evolved over the years from simple, manual systems to fully automatic systems with automatic alignment, auto-handlers, dual spindles and quality monitoring systems. As device technology has evolved, so has the requirement for dicing saw manufacturers to meet the ever-increasing needs for higher precision, greater throughput and reduced damage to the topside and bottom-side edges of the dice. In this chapter, the reader is introduced to the dicing process and made aware of the key issues which must be considered when setting up a die separation process [1, 2].
Lyman R. Clark, Mark Brown, Scott Evans, Steve Bedore, Charles E. Gutentag, Robert A. Sierra

6. Ceramic Chip Carriers

Ceramic chip carriers which utilize area-array interconnections have been used in industry applications for over 30 years. This chapter provides ceramic chip carrier examples for each of the six market applications which include High Performance, Cost Performance, Commodity, Hand Held and Communication, Automotive and Memory. Materials and properties are summarized for standard alumina chip carriers, high-performance materials, thin-film materials, and high-thermal-performance materials. Fabrication processes include comparisons for thick film, dry pressed and multilayer ceramics with and without advanced thin-film wiring. Thin-film wiring provides the highest level of wiring for both Single Chip Modules (SCM) and Multi-chip Modules (MCM). Relative comparisons are also made for availability, cost, characteristics and various application form factors.
John U. Knickerbocker, Thomas F. Redmond

7. Laminate/HDI Die Carriers

The use of more complex components with very high I/O counts has pushed the board fabricator to re-examine techniques for creating smaller vias. Over the last several years, many new or redeveloped processes have appeared on the market. These processes include revised methods of creating holes, such as laser drilling, micro-punching, and mass etching; new methods for additively creating dielectric with via holes using photo-sensitive dielectric materials; and new methods for metallizing the vias such as conductive adhesives and solid post vias. All of these methods share some common traits. They all allow the designer to significantly increase routing density through the use of vias in SMT pads, to reduce size and weight of product, and to improve the electrical performance of the system. These types of boards are generically called, “High Density Interconnects” or HDI.
Happy T. Holden, Donald Barr, Douglas Powell

8. Flip-Chip Die Attach Technology

Wire bonds, tape automated bonding (TAB), and solder-bump, flip-chip connections more popularly referred to as controlled collapsed chip connections or C4 are the three primary chip-to-carrier interconnection technologies currently practiced.
Peter J. Brofman, Karl J. Puttlitz, Kathleen A. Stalter, Charles Woychik

9. Solder Bump Flip-Chip Replacement Technology on Ceramic Carriers

The industry has focused on replacing packaged chips such as pin-in-hole (PIH) and surface-mount components (SMT) on cards or boards. Components which do not pass electrical test or inspection are removed from cards but not chips from single chip packages. In some instances, such as plastic molded packages, removal is not a viable option.
Karl J. Puttlitz, Kathleen A. Stalter

10. Manufacturing Considerations and Tools for Flip Chip Assembly

The complexity of building an area-array manufacturing line is similar to constructing standard electronic-packaging facilities. Decisions which affect the productivity of a manufacturing plant span from initial package design to finished product inspection. As with any manufacturing operation, tradeoffs must be constantly evaluated to achieve an acceptable balance between quality, production, cost and reliability objectives.
David L. Edwards, Barrie C. Campbell, James H. Covell, Kenneth C. Marston, Camille Proietti-Bowne

11. Test and Burn-in Sockets

This chapter addresses the use of area-array socket technology during test and burn-in at the module level. Single chip and multichip modules (SCM, MCM) and their corresponding socket form factors are described ranging from small chip scale packages (CSP) having micro ball grid arrays (MBGA) to very large land grid arrays (LGA) having in excess of 5000 I/Os [1]. Module sizes correspondingly range from tens of millimeters to over one hundred millimeters. Module frequencies of operation range from typical values of approximately 60 MHz for low-end digital applications to multi-gigahertz rf applications. Operating frequency is a primary socket design factor since it has a significant influence on the module contacting method.
Eugene Atwood, Glenn Daves

12. Underfill: The Enabling Technology for Flip-Chip Packaging

Organic polymer reinforcement of area-array solder connections between semiconductor chips and substrates has become an essential part of flip-chip packaging. Although flip-chip interconnection, or controlled collapse chip connection (C4) as it is also known, has a long history prior to the use of any reinforcement [1]; the use of a polymeric material to surround the solder connections beneath attached chips has allowed flip chips with large die footprints and increased neutral point distances to be utilized even with organic chip carriers.
Stephen L. Buchwalter, Maurice E. Edwards, Daniel Gamota, Michael A. Gaynes, Son K. Tran

13. Reliability of Die-Level Interconnections

At the die level, solder interconnections can fail by a number of failure mechanisms if the stress conditions are severe; i.e., fatigue, corrosion, metal migration, electromigration, creep, and thermomigration. Under normal field conditions, non-encapsulated open-array flip chip solder joints attached to alumina chip carriers exhibit the best reliability in the field among all interconnect methods. This, of course, is the result of following established design rules, process parameters and having a firm understanding of the reliability factors associated with flip chip interconnects. Many of these reliability factors are discussed in this chapter. It is necessary to establish an accelerated test capability so that a relatively long life in the field can be predicted on the basis of short term tests. The validity of the tests is achieved by verifying established semi-empirical models and characteristic parameters, and then are employed to predict the field life of joints.
Giulio DiGiacomo, Jasvir S. Jaspal

Package-Level Technology


14. Ceramic and Plastic Pin Grid Array Technology

The technology surrounding integrated circuits has improved drastically since first introduced in 1959. The desire to miniaturize circuits, coupled with increased speed and decreased energy consumption requirements has led to present day highly integrated circuits. To take advantage of the integration enhancements at the die level, much attention is focused on the supporting package performance.
Balaram Ghosal, Richard Sigliano, Y. Kunimatsu

15. Plastic Ball Grid Array

Plastic Ball Grid Array (PBGA) packages are modules constructed utilizing standard printed circuit card and board technologies. The typical PBGA substrate is a thin (less than 0.035 inches) laminate similar to card technologies used for personal computers. Although the interconnections between a chip and substrate are typically wire bonds, flip-chip dice can be attached to PBGA packages as well. PBGA technologies also support chip scale packaging (CSP) discussed in Chapters 18 and 23.
Mark J. Kuzawinski, Thomas R. Homa

16. Tape Ball Grid Array

TAPE Ball Grid Array (TBGA) packages are a family of electronic chip carriers that utilize circuitized flex (tape) as the die carrier mounted to a printed circuit card or board. Previously this family of packages has been referred to by several designations, among them: Area Array Tape Automated Bonding (ATAB) [1], Tape Ball Grid Array (TBGA) [2], fleXBGA1 [3], Wire Bond TBGA (WB TBGA) [4], Signetics TBGA (S-TBGA) [5], Flex TBGA (FTBGA) [6], Star BGA [7]. TBGA is by far the most popular acronym utilized for this family of packages and adopted by the Joint Electronic Device Engineering Council of the Electronic Industry Association (JEDEC) for its standard package outlines [8]. Since the chip carrier is circuitized flex, it has been suggested that these packages more appropriately be referred to as Flex BGAs (FBGA) [9]. Since the standards refer to this package family as TBGAs, the terminology is adopted for this chapter.
Frank Andros

17. Ceramic Ball and Column Grid Arrays

During the 1990s, Ceramic Ball Grid Array (CBGA) and Ceramic Column Grid Array (CCGA) packages moved from development laboratories [1] to volume factory production [2]. The steady growth in the use of these packages has been driven by many factors that fall into one of two major categories: performance or process drivers. These high-interconnection density, surface-mount compatible packages offer many advantages over traditional pinned or peripheral-leaded packages. CBGA and CCGA packages can currently be found in a wide range of applications spanning telecommunications and personal computers to super computers. This chapter serves as a primer on CBGA and CCGA packages. The reasons behind their rise in popularity are explored, including package structure descriptions, range of offerings, established infrastructure and performance attributes. Package interconnection processes are discussed in detail, as are the benefits derived from these packages, as illustrated through several example applications.
Marie S. Cole, Karl J. Puttlitz, Robert Lanzone

18. Chip Scale Package Technology

In the last three decades, many innovative microelectronics packaging and interconnection-related technologies, such as tape automated bonding (TAB), flip chip, multi-chip modules (MCMs), and ball grid arrays (BGAs), have been developed, applied, and demonstrated in a variety of electronic products. The demand for high-density, high-performance, high-function, portable consumer electronics continues almost undiminished. The ever-increasing demand for product performance, versatility, and miniaturization, resulted in significant advances in semiconductor device power, performance and pin count. These, in turn, have imposed significant challenges upon electronic companies to provide even more compact, cost-effective, and reliable products [1,2].
Puligandla Viswanadham, Tom Chung, Steven O. Dunford

19. Assembly of Area Array Components

Surface mount technology (SMT) has become the accepted standard for electronic assembly throughout the world. Surface mount packaging dominates the packaging industry due to the space saving and increased wiring capability achieved by directly mounting components on the surface of a board as opposed to the need for through holes in a printed circuit board (PCB). Cost, performance and ease of assembly have been the drivers in the trend away from DIP (dual-in-line package) packages and PTH (plated through hole) assembly to SMT. SMT packages include a variety of leaded and ball grid array packages all of which are mounted to conductors on the surface of a circuit card (Fig. 19-1). SMT assembly has increased dramatically over the past ten years typically allowing 1000-10,000 soldered connections per board as opposed to 250-4000 connections for similar through-hole assemblies. This chapter describes SMT assembly materials, equipment and process techniques in assembly of area-array or Ball Grid Array (BGA) packages including ball grid arrays (BGAs) and chip scale packages (CSPs).
Cynthia Milkovich

20. Area Array Component Replacement Technology

As surface mount technology advanced from peripheral-leaded to area-array (AA) devices, assembly shops benefited from significant improvements in process yields and component reliability.
Phil Isaacs, Karl J. Puttlitz

21. Product Connector Technology

The use of product connectors has mainly involved high-end applications. Electronic modules normally represent a function, and one or more multichip modules typically are combined on a card or board. It is important that some or all the individual modules be easily separable to permit testing, diagnositcs and field repair, and that the separable connections not functionally degrade the electrical signals [1]. The intent is to preserve the value of a board and its attached components while having the capability to make repairs or upgrades through component exchanges throughout the lifetime of a part. Several early area-array “compression connection” concepts were reported in the mid 1980s/early 1990s that recognized that a disassembly design must also be capable of high I/O density to accommodate ever increasing I/O counts (i.e., extendible to decreasing pitches).
Karl J. Puttlitz, Lewis S. Goldmann

22. Board-Level Area Array Interconnect Reliability

The objective of reliability engineering is to provide the capability of predicting the percentage of field cumulative failures at the end of life with a certain degree of confidence, based on the statistical distribution of the data and on the acceleration factor determined by testing. There are, therefore, bounds on confidence limits which accompany the median time-to-failure, the standard deviation of the data and projected fail fraction. As with the die-level, board level area-array solder joint, tests are used to verify semi-empirical models based on failure data.
Thomas H. Koschmieder, Andrew J. Mawer, Giülio Di Giacomo, Jasvir S. Jaspal

23. Chip Scale Package Assembly Reliability

Emerging chip scale packages (CSPs) and miniature versions of ball grid arrays (BGAs), are competing with bare die flip chip assemblies. CSP is an important miniature electronic package technology utilizing low pin counts, without the attendant handling and processing problems of low peripheral leaded packages such as thin small outline packages (TSOPs) and high-I/O (input/ output) quad flat packages (QFPs). Advantages include self-alignment capability during assembly reflow process and better lead (ball) rigidity. Reliability data and inspection techniques are needed for CSP acceptance especially for high-reliability applications.
Reza Ghaffarian

Base Technology


24. Area-array Design Principles

The advancement in silicon device technology with its associated frequency increases is having a major affects across all electronic market segments. These range from basic consumer electronics to high-performance computer and communications systems. As semiconductor ground rules and densities continue to improve, the resulting smaller chips are enabling more and more function to be integrated on an individual die; thus, enabling even smaller and lower cost chips than exist today. These relatively inexpensive parts are finding their way into affordable electronic products such as personal computers, cellular telephones, and palmtop computers.
George Katopis, Dale Becker, Evan Davidson, Michael Nealon

25. Area Array Leverages: Why and How to Choose a Package

Performance is an attribute that defines how well a given requirement is satisfied and is predicated on priority so may depend upon one or a multiplicity of factors. Among those most often considered in microelectronic packaging are thermal and electrical characteristics, size, cost and reliability. The details of array technology at the die, module and board levels have been discussed in the preceding chapters. It is the purpose of this chapter to provide comparative data and some guidance in how to select a technology in consideration of the various options and strategies available based upon the application.
David L. Thomas, Daniel O’Connor, Jeffrey A. Zitz

26. Interconnections for High-Frequency Applications

The drive towards more and more wireless communication for various purposes increases the need for electronic packages capable of ever-higher operating frequencies. This chapter gives an overview of die and package interconnects suitable for high-frequency operation, i.e., GHz range. Of particular interest are the challenges in moving from more traditional interconnect methods to gallium arsenide flip-chip technology.
K. Boustedt

27. Thermal Performance

A robust package thermal design achieves many objectives. Although the primary objective is to maintain a proper module operating temperature range many other objectives must be realized simultaneously to be useful. The module thermal design must be integral with the system-thermal design, whether the system is a mainframe computer, personal computer, video game or a pager. Thermal-solution costs must be consistent with overall system costs. Thermal-solution components should be readily and commercially available, easily manufactured and inspectable for quality. They must be capable of surviving the rigors of card and system manufacturing, shipping, storage and use, often providing many years of subsequent service under radically changing environmental conditions with little or no maintenance. Many must be designed for disassembly for in-plant or in-field rework, reclaim or upgrade.
Jeffrey A. Zitz, Randall G. Kemink, Bahgat Sammakia, Sanjeev Sathe, David J. Womac

28. Metallurgical Factors

Interconnects between the various levels of an electronic package must form both an electrical and a mechanical joint. The traditional material to create this interconnect has been a Sn-Pb solder alloy. For through-hole technology, solder mechanically attaches leads to a printed wiring board. Sn-Pb solder was chosen because it has a relatively low melting point, good wetting behavior, good electrical conductivity and can be used in hierarchical soldering. Hierarchical soldering is the utilization of a solder that has a lower melting point temperature than all others that preceded it. The lower temperature solder must have a working temperature sufficiently low so that it does not melt a higher temperature interconnect. The melting temperature range for Sn-Pb solders is from 310°C for Sn-97Pb to 183°C for eutectic Sn-Pb.
D. R. Frear, K.-N. Tu


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