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Journal of Electronic Testing
Erschienen in: Journal of Electronic Testing 4/2020

19.07.2020

Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit

verfasst von: Mamoru Ishizaka, Michihiro Shintani, Michiko Inoue

Erschienen in: Journal of Electronic Testing | Ausgabe 4/2020

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Abstract

Resistive random-access memory (ReRAM) has several attractive features such as high storage density and high switching frequency with low power consumption. It is hence regarded as the most promising nonvolatile memory material. However, a memristor, which is a primitive component of the ReRAM-based memory, has much lower write endurance. Hence, an error-correcting code (ECC) circuit is indispensable for realizing reliable ReRAM storage. Accordingly, we propose a hybrid CMOS/memristor-based ECC circuit. In the proposed circuit, the blocks with high-frequency write operations are implemented using the conventional CMOS technology and the other blocks are implemented using the memristors to maintain a balance between the area overhead and reliability. Through numerical experiments, we demonstrate that the proposed ECC circuit achieves smaller area and higher reliability than the full memristor-based ECC circuits and achieves much smaller area while preserving the reliability compared with the full CMOS-based ECC circuits.
Vorheriger Artikel Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables
Nächster Artikel Design of an Integrated System for On-line Test and Diagnosis of Rotary Actuators

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Metadaten
Titel
Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit
verfasst von
Mamoru Ishizaka
Michihiro Shintani
Michiko Inoue
Publikationsdatum
19.07.2020
Verlag
Springer US
Erschienen in
Journal of Electronic Testing / Ausgabe 4/2020
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-020-05892-3

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