Area-Efficient Automated Logic Design with Monte-Carlo Tree Search

Automated logic design for digital circuits significantly reduces manual effort in chip design processes, as logic design &verification are the most manual-intensive periods in the entire chip design flow. Without human programming, the Hardware Design Language (HDL) codes, combined with state-of-the-art iterative data-driven methods, monotonically reduce error rates using input-output examples to ensure design functionality. This approach enables the design of large-scale circuits, such as RISC-V CPUs, for tapeout. However, these data-driven methods can lead to significant area overhead due to a lack of prior knowledge about the circuit structure. This paper proposes a Monte Carlo Tree Search (MCTS) based approach, A-BSD, to optimize the area overhead of automated logic design while maintaining the ability to design accurately. The key insight is that, with specific automated circuit design parameters, the area overhead can be significantly reduced. Although the potential parameter-design space is vast and challenging to explore, we formulate automated circuit design as a Monte-Carlo Tree Search problem to reduce the computing complexity with two novel Operations in the design process, i.e., (1) layer insertion and (2) variable switching. To further reduce the costly computational complexity, we train an efficient evaluation model on randomly generated circuits with fast approximate simulation results to guide the evaluation of the design area overhead. Experimental results on standard benchmark circuits demonstrate that our method reduces the design area by 26% compared to the state-of-the-art baselines while maintaining design functionality.