An Application Specific Inflexible FPGA (ASIF) is an FPGA with reduced flexibility that can implement a set of application circuits which will operate at mutually exclusive times. An ASIF that is reduced from a heterogeneous FPGA is called as a Heterogeneous-ASIF. A Heterogeneous-ASIF can contain hard-block such as Multipliers, Adders, RAMS or even smaller Gates. A set of application circuits are efficiently placed and routed to minimize total routing switches required by the heterogeneous FPGA architecture. Different floor-planning techniques are used to optimize the position of hard-blocks on the FPGA architecture. Later, all unused routing switches are removed from the FPGA to generate a Heterogeneous-ASIF. This work shows that a standard-cell based Heterogeneous-ASIF using Multipliers, Adders and Look-Up Tables for a set of 10 opencores application circuits is 85% smaller in area than a single-driver FPGA using the same type of blocks. This Heterogeneous-ASIF is only 24% larger than the sum of areas of their standard-cell based ASIC versions. If the Look-Up Tables are replaced by a set of repeatedly used hard logic gates (such as AND gate, OR gate, Flip- Flops etc), the ASIF becomes 89% smaller than the FPGA and 3% smaller than the sum of ASICs. The area gap between ASIF and sum of ASICs can be further reduced if repeatedly used groups of standard-cell logic gates in an ASIF are designed in full-custom. One of the major advantages of an ASIF is that just like an FPGA, an ASIF can also be reprogrammed to execute new or modified circuits, but at a very limited scale. A new CAD flow is presented to map application circuits on an ASIF.
Weitere Kapitel dieses Buchs durch Wischen aufrufen
Bitte loggen Sie sich ein, um Zugang zu diesem Inhalt zu erhalten
Sie möchten Zugang zu diesem Inhalt erhalten? Dann informieren Sie sich jetzt über unsere Produkte:
- ASIF using Heterogeneous Logic Blocks
- Springer New York