Skip to main content

2021 | OriginalPaper | Buchkapitel

19. Asynchronous Circuits and Their Applications in Hardware Security

verfasst von : Eslam Yahya Tawfik, Waleed Khalil

Erschienen in: Emerging Topics in Hardware Security

Verlag: Springer International Publishing

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

Asynchronous circuits are increasingly used as an efficient countermeasure for a wide range of threats in the microelectronics industry. This chapter provides a tutorial on the basic concepts of asynchronous design, with an elaboration on their potential benefits and drawbacks. The chapter also provides a literature survey on applying asynchronous circuits to hardware security, potential security flaws in asynchronous design, and a discussion on proposed mitigation techniques.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Literatur
1.
Zurück zum Zitat The Cost of Malicious Cyber Activity to the U.S. Economy, The Council of Economic Advisers, February 2018 The Cost of Malicious Cyber Activity to the U.S. Economy, The Council of Economic Advisers, February 2018
2.
Zurück zum Zitat Y. Zhou, D. Feng, Side-channel attacks: Ten years after its publication and the impacts on cryptographic module security testing. IACR Cryptol. ePrint Arch. 2005, 388 (2005) Y. Zhou, D. Feng, Side-channel attacks: Ten years after its publication and the impacts on cryptographic module security testing. IACR Cryptol. ePrint Arch. 2005, 388 (2005)
3.
Zurück zum Zitat M. Tehranipoor, C. Wang (eds.), Introduction to Hardware Security and Trust (Springer, 2011) M. Tehranipoor, C. Wang (eds.), Introduction to Hardware Security and Trust (Springer, 2011)
4.
Zurück zum Zitat R. Focardi, R. Gorrieri (eds.), Foundations of Security Analysis and Design: Tutorial Lectures (Springer, 2003) R. Focardi, R. Gorrieri (eds.), Foundations of Security Analysis and Design: Tutorial Lectures (Springer, 2003)
5.
Zurück zum Zitat T. Popp, S. Mangard, E. Oswald, Power analysis attacks and countermeasures. IEEE Des. Test Comput. 24(6), 535–543 (2007)CrossRef T. Popp, S. Mangard, E. Oswald, Power analysis attacks and countermeasures. IEEE Des. Test Comput. 24(6), 535–543 (2007)CrossRef
6.
Zurück zum Zitat P. Kocher, J. Jaffe, B. Jun, Differential power analysis. Proceedings of the 19th annual international cryptology conference on Advances in Cryptology, in CRYPTO ’99, (2017), pp. 388–397 P. Kocher, J. Jaffe, B. Jun, Differential power analysis. Proceedings of the 19th annual international cryptology conference on Advances in Cryptology, in CRYPTO ’99, (2017), pp. 388–397
7.
Zurück zum Zitat S. Mangard, E. Oswald, T. Popp, Power Analysis Attacks: Revealing the Secrets of Smart Cards (Springer, New York, 2010)MATH S. Mangard, E. Oswald, T. Popp, Power Analysis Attacks: Revealing the Secrets of Smart Cards (Springer, New York, 2010)MATH
8.
Zurück zum Zitat W. Shan, F. Xingyuan, X. Zhipeng, A secure reconfigurable crypto IC with countermeasures against SPA, DPA, and EMA. IEEE Trans. Comp. Aided Des. Integr. Circ. Syst. 34(7), 1201–1205 (2015)CrossRef W. Shan, F. Xingyuan, X. Zhipeng, A secure reconfigurable crypto IC with countermeasures against SPA, DPA, and EMA. IEEE Trans. Comp. Aided Des. Integr. Circ. Syst. 34(7), 1201–1205 (2015)CrossRef
9.
Zurück zum Zitat C. Giraud, R.S.A. An, Implementation resistant to fault attacks and to simple power analysis. IEEE Trans. Comput. 55(9), 1116–1120 (2006)CrossRef C. Giraud, R.S.A. An, Implementation resistant to fault attacks and to simple power analysis. IEEE Trans. Comput. 55(9), 1116–1120 (2006)CrossRef
10.
Zurück zum Zitat G. Ratanpal, R. Williams, T. Blalock, An on-chip signal suppression countermeasure to power analysis attacks. IEEE Trans. Dependable Secure Comput. 1(3), 179–189 (2004)CrossRef G. Ratanpal, R. Williams, T. Blalock, An on-chip signal suppression countermeasure to power analysis attacks. IEEE Trans. Dependable Secure Comput. 1(3), 179–189 (2004)CrossRef
11.
Zurück zum Zitat J. Sparsø, Principles of Asynchronous Circuit Design: A Systems Perspective (Kluwer, Boston, 2001)CrossRef J. Sparsø, Principles of Asynchronous Circuit Design: A Systems Perspective (Kluwer, Boston, 2001)CrossRef
12.
Zurück zum Zitat J. Sparsø, Introduction to Asynchronous Circuit Design (DTU Compute, Technical University of Denmark, 2020) J. Sparsø, Introduction to Asynchronous Circuit Design (DTU Compute, Technical University of Denmark, 2020)
13.
Zurück zum Zitat E. Yahya, M. Renaudin, QDI latches characteristics and asynchronous linear-pipeline performance analysis, in Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, ed. by J. Vounckx, N. Azemard, P. Maurine, vol. 4148, (Springer, Berlin/Heidelberg, 2006) E. Yahya, M. Renaudin, QDI latches characteristics and asynchronous linear-pipeline performance analysis, in Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, ed. by J. Vounckx, N. Azemard, P. Maurine, vol. 4148, (Springer, Berlin/Heidelberg, 2006)
14.
Zurück zum Zitat H. Zakaria, E. Yahya, L. Fesquet, Self adaption in SoCs, in Autonomic Networking-on-Chip: Bio-inspired Specification, Development, and Verification, ed. by P. Cong-Vinh, (CRC Press, Boca Raton, 2012) H. Zakaria, E. Yahya, L. Fesquet, Self adaption in SoCs, in Autonomic Networking-on-Chip: Bio-inspired Specification, Development, and Verification, ed. by P. Cong-Vinh, (CRC Press, Boca Raton, 2012)
15.
Zurück zum Zitat E. Yahya, L. Fesquet, Asynchronous design: A promising paradigm for electronic circuits and systems, in 2009 16th IEEE International Conference on Electronics, Circuits and Systems – (ICECS 2009), (2009) E. Yahya, L. Fesquet, Asynchronous design: A promising paradigm for electronic circuits and systems, in 2009 16th IEEE International Conference on Electronics, Circuits and Systems – (ICECS 2009), (2009)
17.
Zurück zum Zitat M. Davies, A. Lines, J. Dama, A. Gravel, R. Southworth, G. Dimou, P. Beerel, A 72-port 10G Ethernet switch/router using quasi-delay-insensitive asynchronous design, in 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems, 12 May 2014, (IEEE), pp. 103–104 M. Davies, A. Lines, J. Dama, A. Gravel, R. Southworth, G. Dimou, P. Beerel, A 72-port 10G Ethernet switch/router using quasi-delay-insensitive asynchronous design, in 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems, 12 May 2014, (IEEE), pp. 103–104
18.
Zurück zum Zitat X. Fan, O. Schrape, M. Marinkovic, P. Dähnert, M. Krstic, E. Grass, GALS design for spectral peak attenuation of switching current, in 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems, 19 May 2013, (IEEE), pp. 83–90 X. Fan, O. Schrape, M. Marinkovic, P. Dähnert, M. Krstic, E. Grass, GALS design for spectral peak attenuation of switching current, in 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems, 19 May 2013, (IEEE), pp. 83–90
19.
Zurück zum Zitat Sheikh BR, Manohar R. An operand-optimized asynchronous IEEE 754 double-precision floating-point adder. In 2010 IEEE Symposium on Asynchronous Circuits and Systems, 3 May 2010 (pp. 151-162). IEEE Sheikh BR, Manohar R. An operand-optimized asynchronous IEEE 754 double-precision floating-point adder. In 2010 IEEE Symposium on Asynchronous Circuits and Systems, 3 May 2010 (pp. 151-162). IEEE
20.
Zurück zum Zitat B. Hollosi, M. Barlow, G. Fu, C. Lee, J. Di, S.C. Smith, H.A. Mantooth, M. Schupbach, Delay-insensitive asynchronous ALU for cryogenic temperature environments, in 2008 51st Midwest Symposium on Circuits and Systems, 10 August 2008, (IEEE), pp. 322–325 B. Hollosi, M. Barlow, G. Fu, C. Lee, J. Di, S.C. Smith, H.A. Mantooth, M. Schupbach, Delay-insensitive asynchronous ALU for cryogenic temperature environments, in 2008 51st Midwest Symposium on Circuits and Systems, 10 August 2008, (IEEE), pp. 322–325
21.
Zurück zum Zitat A. Bailey, A. Al Zahrani, G. Fu, J. Di, S. Smith, Multi-threshold asynchronous circuit design for ultra-low power. J. Low Power Electron. 4(3), 337–348 (2008)CrossRef A. Bailey, A. Al Zahrani, G. Fu, J. Di, S. Smith, Multi-threshold asynchronous circuit design for ultra-low power. J. Low Power Electron. 4(3), 337–348 (2008)CrossRef
22.
Zurück zum Zitat R. Zhou, K.S. Chong, B.H. Gwee, J.S. Chang, A low overhead quasi-delay-insensitive (QDI) asynchronous data path synthesis based on microcell-interleaving genetic algorithm (MIGA). IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 33(7), 989–1002 (2014)CrossRef R. Zhou, K.S. Chong, B.H. Gwee, J.S. Chang, A low overhead quasi-delay-insensitive (QDI) asynchronous data path synthesis based on microcell-interleaving genetic algorithm (MIGA). IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 33(7), 989–1002 (2014)CrossRef
23.
Zurück zum Zitat W.G. Ho, K.S. Chong, B.H. Gwee, J.S. Chang, M.F. Yee, A power-efficient integrated input/output completion detection circuit for asynchronous-logic quasi-delay-insensitive pre-charged half-buffer, in 2011 International Symposium on Integrated Circuits, 12 December 2011, (IEEE), pp. 376–379 W.G. Ho, K.S. Chong, B.H. Gwee, J.S. Chang, M.F. Yee, A power-efficient integrated input/output completion detection circuit for asynchronous-logic quasi-delay-insensitive pre-charged half-buffer, in 2011 International Symposium on Integrated Circuits, 12 December 2011, (IEEE), pp. 376–379
24.
Zurück zum Zitat E. Yahya, L. Fesquet, Y. Ismail, M. Renaudin, Statistical static timing analysis of conditional asynchronous circuits using model-based simulation, in 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems, 19 May 2013, (IEEE), pp. 67–74 E. Yahya, L. Fesquet, Y. Ismail, M. Renaudin, Statistical static timing analysis of conditional asynchronous circuits using model-based simulation, in 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems, 19 May 2013, (IEEE), pp. 67–74
25.
Zurück zum Zitat A. Yakovlev, P. Vivet, M. Renaudin, Advances in asynchronous logic: From principles to GALS & NoC, recent industry applications, and commercial CAD tools, in 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 18 March 2013, (IEEE), pp. 1715–1724 A. Yakovlev, P. Vivet, M. Renaudin, Advances in asynchronous logic: From principles to GALS & NoC, recent industry applications, and commercial CAD tools, in 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 18 March 2013, (IEEE), pp. 1715–1724
26.
Zurück zum Zitat M. Renaudin, A. Fonkoua, Tiempo asynchronous circuits system verilog modeling language, in 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, 7 May 2012, (IEEE), pp. 105–112 M. Renaudin, A. Fonkoua, Tiempo asynchronous circuits system verilog modeling language, in 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, 7 May 2012, (IEEE), pp. 105–112
27.
Zurück zum Zitat N.E.C. Akkaya, B. Erbagci, R. Carley, K. Mai, A DPA-resistant self-timed three-phase dual-rail pre-charge logic family. IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2015, pp. 112–117 N.E.C. Akkaya, B. Erbagci, R. Carley, K. Mai, A DPA-resistant self-timed three-phase dual-rail pre-charge logic family. IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2015, pp. 112–117
28.
Zurück zum Zitat S. Guilley, L. Sauvage, F. Flament, V.-N. Vong, P. Hoogvorst, R. Pacalet, Evaluation of power constant dual-rail logics countermeasures against DPA with design time security metrics. IEEE Trans. Comput. 59(9), 1250–1263 (2010)MathSciNetCrossRef S. Guilley, L. Sauvage, F. Flament, V.-N. Vong, P. Hoogvorst, R. Pacalet, Evaluation of power constant dual-rail logics countermeasures against DPA with design time security metrics. IEEE Trans. Comput. 59(9), 1250–1263 (2010)MathSciNetCrossRef
29.
Zurück zum Zitat N.-H. Zhu, Y.-J. Zhou, H.-M. Liu, Employing symmetric dual-rail logic to thwart LPA attack. IEEE Embed. Syst. Lett. 5(4), 61–64 (2013)CrossRef N.-H. Zhu, Y.-J. Zhou, H.-M. Liu, Employing symmetric dual-rail logic to thwart LPA attack. IEEE Embed. Syst. Lett. 5(4), 61–64 (2013)CrossRef
30.
Zurück zum Zitat Y. Monnet, M. Renaudin, R. Leveugle, Designing resistant circuits against malicious faults injection using asynchronous logic. IEEE Trans. Comput. 55(9), 1104–1115 (2006)CrossRef Y. Monnet, M. Renaudin, R. Leveugle, Designing resistant circuits against malicious faults injection using asynchronous logic. IEEE Trans. Comput. 55(9), 1104–1115 (2006)CrossRef
31.
Zurück zum Zitat Q. Ou, F. Luo, S. Li, L. Chen, Circuit level defences against fault attacks in pipelined NCL circuits. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23(9), 1903–1913 (2015)CrossRef Q. Ou, F. Luo, S. Li, L. Chen, Circuit level defences against fault attacks in pipelined NCL circuits. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23(9), 1903–1913 (2015)CrossRef
32.
Zurück zum Zitat J.J. Fournier, S. Moore, H. Li, R. Mullins, G. Taylor, Security evaluation of asynchronous circuits, in International Workshop on Cryptographic Hardware and Embedded Systems, 8 September 2003, (Heidelberg, Springer/Berlin), pp. 137–151 J.J. Fournier, S. Moore, H. Li, R. Mullins, G. Taylor, Security evaluation of asynchronous circuits, in International Workshop on Cryptographic Hardware and Embedded Systems, 8 September 2003, (Heidelberg, Springer/Berlin), pp. 137–151
33.
Zurück zum Zitat K.J. Kulikowski, M. Su, A. Smirnov, A. Taubin, M.G. Karpovsky, D. MacDonald, Delay insensitive encoding and power analysis: a balancing act [cryptographic hardware protection], in 11th IEEE International Symposium on Asynchronous Circuits and Systems, 14 March 2005, (IEEE), pp. 116–125 K.J. Kulikowski, M. Su, A. Smirnov, A. Taubin, M.G. Karpovsky, D. MacDonald, Delay insensitive encoding and power analysis: a balancing act [cryptographic hardware protection], in 11th IEEE International Symposium on Asynchronous Circuits and Systems, 14 March 2005, (IEEE), pp. 116–125
34.
Zurück zum Zitat G.F. Bouesse, M. Renaudin, S. Dumont, F. Germain, DPA on quasi delay insensitive asynchronous circuits: formalization and improvement. Des. Autom. Test Eur. 1, 424–429 (2005)CrossRef G.F. Bouesse, M. Renaudin, S. Dumont, F. Germain, DPA on quasi delay insensitive asynchronous circuits: formalization and improvement. Des. Autom. Test Eur. 1, 424–429 (2005)CrossRef
35.
Zurück zum Zitat D. Sokolov, J. Murphy, A. Bystrov, A. Yakovlev, Improving the security of dual-rail circuits, in International Workshop on Cryptographic Hardware and Embedded Systems, 11 August 2004, (Heidelberg, Springer/Berlin), pp. 282–297 D. Sokolov, J. Murphy, A. Bystrov, A. Yakovlev, Improving the security of dual-rail circuits, in International Workshop on Cryptographic Hardware and Embedded Systems, 11 August 2004, (Heidelberg, Springer/Berlin), pp. 282–297
36.
Zurück zum Zitat N. Liu, K.S. Chong, W.G. Ho, B.H. Gwee, J.S. Chang, Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications, in 2016 Design, Automation & Test in Europe Conference & Exhibition, 14 March 2016, (IEEE), pp. 850–853 N. Liu, K.S. Chong, W.G. Ho, B.H. Gwee, J.S. Chang, Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications, in 2016 Design, Automation & Test in Europe Conference & Exhibition, 14 March 2016, (IEEE), pp. 850–853
37.
Zurück zum Zitat J. Wu, Y. Shi, M. Choi, Measurement and evaluation of power analysis attacks on asynchronous S-box. IEEE Trans. Instrum. Measur. 61(10), 2765–2775 (2012)CrossRef J. Wu, Y. Shi, M. Choi, Measurement and evaluation of power analysis attacks on asynchronous S-box. IEEE Trans. Instrum. Measur. 61(10), 2765–2775 (2012)CrossRef
38.
Zurück zum Zitat P. Kocher, J. Jaffe, B. Jun, Differential power analysis, in Annual International Cryptology Conference, 15 August 1999, (Springer, Berlin/Heidelberg), pp. 388–397 P. Kocher, J. Jaffe, B. Jun, Differential power analysis, in Annual International Cryptology Conference, 15 August 1999, (Springer, Berlin/Heidelberg), pp. 388–397
39.
Zurück zum Zitat D. Das, S. Maity, S.B. Nasir, S. Ghosh, A. Raychowdhury, S. Sen, High efficiency power side-channel attack immunity using noise injection in attenuated signature domain, in 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 1 May 2017, (IEEE), pp. 62–67 D. Das, S. Maity, S.B. Nasir, S. Ghosh, A. Raychowdhury, S. Sen, High efficiency power side-channel attack immunity using noise injection in attenuated signature domain, in 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 1 May 2017, (IEEE), pp. 62–67
40.
Zurück zum Zitat D. Das, S. Maity, S.B. Nasir, S. Ghosh, A. Raychowdhury, S. Sen, ASNI: Attenuated signature noise injection for low-overhead power side-channel attack immunity. IEEE Trans. Circ. Syst. I: Regul. Pap. 65(10), 3300–3311 (2018) D. Das, S. Maity, S.B. Nasir, S. Ghosh, A. Raychowdhury, S. Sen, ASNI: Attenuated signature noise injection for low-overhead power side-channel attack immunity. IEEE Trans. Circ. Syst. I: Regul. Pap. 65(10), 3300–3311 (2018)
41.
Zurück zum Zitat A. Singh, M. Kar, S. Mathew, A. Rajan, V. De, S. Mukhopadhyay, 25.3 A 128b AES engine with higher resistance to power and electromagnetic side-channel attacks enabled by a security-aware integrated all-digital low-dropout regulator, in 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 17 February 2019, (IEEE), pp. 404–406 A. Singh, M. Kar, S. Mathew, A. Rajan, V. De, S. Mukhopadhyay, 25.3 A 128b AES engine with higher resistance to power and electromagnetic side-channel attacks enabled by a security-aware integrated all-digital low-dropout regulator, in 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 17 February 2019, (IEEE), pp. 404–406
42.
Zurück zum Zitat M. Kar, A. Singh, S.K. Mathew, A. Rajan, V. De, S. Mukhopadhyay, Reducing power side-channel information leakage of AES engines using fully integrated inductive voltage regulator. IEEE J. Solid-State Circ. 53(8), 2399–2414 (2018)CrossRef M. Kar, A. Singh, S.K. Mathew, A. Rajan, V. De, S. Mukhopadhyay, Reducing power side-channel information leakage of AES engines using fully integrated inductive voltage regulator. IEEE J. Solid-State Circ. 53(8), 2399–2414 (2018)CrossRef
43.
Zurück zum Zitat K. Tiri, I. Verbauwhede, A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation, in Proceedings Design, Automation and Test in Europe Conference and Exhibition, 16 February 2004, vol. 1, (IEEE), pp. 246–251 K. Tiri, I. Verbauwhede, A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation, in Proceedings Design, Automation and Test in Europe Conference and Exhibition, 16 February 2004, vol. 1, (IEEE), pp. 246–251
45.
Zurück zum Zitat F. Bouesse, M. Renaudin, G. Sicard, Improving DPA resistance of quasi delay insensitive circuits using randomly time-shifted acknowledgment signals, in Vlsi-Soc: From Systems to Silicon, 2007, (Springer, Boston), pp. 11–24 F. Bouesse, M. Renaudin, G. Sicard, Improving DPA resistance of quasi delay insensitive circuits using randomly time-shifted acknowledgment signals, in Vlsi-Soc: From Systems to Silicon, 2007, (Springer, Boston), pp. 11–24
46.
Zurück zum Zitat M.C. Hsueh, T.K. Tsai, R.K. Iyer, Fault injection techniques and tools. Computer 30(4), 75–82 (1997)CrossRef M.C. Hsueh, T.K. Tsai, R.K. Iyer, Fault injection techniques and tools. Computer 30(4), 75–82 (1997)CrossRef
47.
Zurück zum Zitat W. Jang, A.J. Martin, Seu-tolerant qdi circuits [quasi delay-insensitive asynchronous circuits], in 11th IEEE International Symposium on Asynchronous Circuits and Systems, 14 March 2005, (IEEE), pp. 156–165 W. Jang, A.J. Martin, Seu-tolerant qdi circuits [quasi delay-insensitive asynchronous circuits], in 11th IEEE International Symposium on Asynchronous Circuits and Systems, 14 March 2005, (IEEE), pp. 156–165
48.
Zurück zum Zitat E. Yahya, H. Zakaria, Y. Ismail, Deadlock detection in conditional asynchronous circuits under mismatched branch selection, in 2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 6 December 2015, (IEEE), pp. 596–600 E. Yahya, H. Zakaria, Y. Ismail, Deadlock detection in conditional asynchronous circuits under mismatched branch selection, in 2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 6 December 2015, (IEEE), pp. 596–600
49.
Zurück zum Zitat Y. Monnet, M. Renaudin, R. Leveugle, Designing resistant circuits against malicious faults injection using asynchronous logic. IEEE Trans. Comput. 55(9), 1104–1115 (2006)CrossRef Y. Monnet, M. Renaudin, R. Leveugle, Designing resistant circuits against malicious faults injection using asynchronous logic. IEEE Trans. Comput. 55(9), 1104–1115 (2006)CrossRef
50.
Zurück zum Zitat R.P. Bastos, G. Sicard, F. Kastensmidt, M. Renaudin, R. Reis, Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies. Microelectron. Reliab. 50(9-11), 1241–1246 (2010)CrossRef R.P. Bastos, G. Sicard, F. Kastensmidt, M. Renaudin, R. Reis, Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies. Microelectron. Reliab. 50(9-11), 1241–1246 (2010)CrossRef
51.
Zurück zum Zitat E. Yahya, O. Elissati, H. Zakaria, L. Fesquet, M. Renaudin, Programmable/stoppable oscillator based on self-timed rings, in 2009 15th IEEE Symposium on Asynchronous Circuits and Systems, 17 May 2009, (IEEE), pp. 3–12 E. Yahya, O. Elissati, H. Zakaria, L. Fesquet, M. Renaudin, Programmable/stoppable oscillator based on self-timed rings, in 2009 15th IEEE Symposium on Asynchronous Circuits and Systems, 17 May 2009, (IEEE), pp. 3–12
52.
Zurück zum Zitat O. Elissati, S. Rieubon, E. Yahya, L. Fesquet, Self-timed rings: a promising solution for generating high-speed high-resolution low-phase noise clocks, in IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip, 27 September 2010, (Springer, Berlin/Heidelberg), pp. 22–42 O. Elissati, S. Rieubon, E. Yahya, L. Fesquet, Self-timed rings: a promising solution for generating high-speed high-resolution low-phase noise clocks, in IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip, 27 September 2010, (Springer, Berlin/Heidelberg), pp. 22–42
53.
Zurück zum Zitat A. Cherkaoui, V. Fischer, A. Aubert, L. Fesquet, A self-timed ring based true random number generator, in 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems, 19 May 2013, (IEEE), pp. 99–106 A. Cherkaoui, V. Fischer, A. Aubert, L. Fesquet, A self-timed ring based true random number generator, in 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems, 19 May 2013, (IEEE), pp. 99–106
54.
Zurück zum Zitat Y. Zhang, J. Jiang, Q. Wang, N. Guan, A self-timed ring based true random number generator on FPGA, in 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), October 2018, (IEEE), pp. 1–3 Y. Zhang, J. Jiang, Q. Wang, N. Guan, A self-timed ring based true random number generator on FPGA, in 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), October 2018, (IEEE), pp. 1–3
55.
Zurück zum Zitat K. Inaba, T. Yoneda, T. Kanamoto, A. Kurokawa, M. Imai, Hardware Trojan insertion and detection in asynchronous circuits, in 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 12 May 2019, (IEEE), pp. 134–143 K. Inaba, T. Yoneda, T. Kanamoto, A. Kurokawa, M. Imai, Hardware Trojan insertion and detection in asynchronous circuits, in 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 12 May 2019, (IEEE), pp. 134–143
56.
Zurück zum Zitat M. Singh, S.M. Nowick, MOUSETRAP: high-speed transition-signaling asynchronous pipelines. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 15(6), 684–698 (2007)CrossRef M. Singh, S.M. Nowick, MOUSETRAP: high-speed transition-signaling asynchronous pipelines. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 15(6), 684–698 (2007)CrossRef
57.
Zurück zum Zitat S. Chowdhury, R. Acharya, W. Boullion, A. Felder, M. Howard, J. Di, D. Forte, A weak asynchronous RESet (ARES) PUF using start-up characteristics of null conventional logic gates, in IEEE International Test Conference (ITC), (IEEE, 2020) S. Chowdhury, R. Acharya, W. Boullion, A. Felder, M. Howard, J. Di, D. Forte, A weak asynchronous RESet (ARES) PUF using start-up characteristics of null conventional logic gates, in IEEE International Test Conference (ITC), (IEEE, 2020)
59.
Zurück zum Zitat Yu A, Brée DS. A clock-less implementation of the AES resists to power and timing attacks. In International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004, 5 April 2004 (2, pp. 525-532). IEEE Yu A, Brée DS. A clock-less implementation of the AES resists to power and timing attacks. In International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004, 5 April 2004 (2, pp. 525-532). IEEE
60.
Zurück zum Zitat G.F. Bouesse, M. Renaudin, A. Witon, F. Germain, A clock-less low-voltage AES crypto-processor, in Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005, 12 September 2005, (IEEE), pp. 403–406 G.F. Bouesse, M. Renaudin, A. Witon, F. Germain, A clock-less low-voltage AES crypto-processor, in Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005, 12 September 2005, (IEEE), pp. 403–406
61.
Zurück zum Zitat Z. Liu, Y. Zeng, X. Zou, Y. Han, Y. Chen, A high-security and low-power AES S-box full-custom design for wireless sensor network, in 2007 International Conference on Wireless Communications, Networking and Mobile Computing, 21 September 2007, (IEEE), pp. 2499–2502 Z. Liu, Y. Zeng, X. Zou, Y. Han, Y. Chen, A high-security and low-power AES S-box full-custom design for wireless sensor network, in 2007 International Conference on Wireless Communications, Networking and Mobile Computing, 21 September 2007, (IEEE), pp. 2499–2502
62.
Zurück zum Zitat D. Shang, F. Burns, A. Bystrov, A. Koelmans, D. Sokolov, A. Yakovlev, High-security asynchronous circuit implementation of AES. IEEE Proc. Comput. Digit. Tech. 153(2), 71–77 (2006)CrossRef D. Shang, F. Burns, A. Bystrov, A. Koelmans, D. Sokolov, A. Yakovlev, High-security asynchronous circuit implementation of AES. IEEE Proc. Comput. Digit. Tech. 153(2), 71–77 (2006)CrossRef
63.
Zurück zum Zitat C.T. Otero, J. Tse, R. Manohar, AES hardware-software co-design in WSN, in 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems, 4 May 2015, (IEEE), pp. 85–92 C.T. Otero, J. Tse, R. Manohar, AES hardware-software co-design in WSN, in 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems, 4 May 2015, (IEEE), pp. 85–92
65.
Zurück zum Zitat N. Elmeligy, M. Amin, E. Yahya, Y. Ismail, 130 nm low power asynchronous AES core. IEEE International Symposium on Circuits & Systems (ISCAS). 2017 N. Elmeligy, M. Amin, E. Yahya, Y. Ismail, 130 nm low power asynchronous AES core. IEEE International Symposium on Circuits & Systems (ISCAS). 2017
66.
Zurück zum Zitat F. Charot, E. Yahya, C. Wagner, Efficient modular-pipelined AES implementation in counter mode on ALTERA FPGA, in International Conference on Field Programmable Logic and Applications, 1 September 2003, (Springer, Berlin/Heidelberg), pp. 282–291 F. Charot, E. Yahya, C. Wagner, Efficient modular-pipelined AES implementation in counter mode on ALTERA FPGA, in International Conference on Field Programmable Logic and Applications, 1 September 2003, (Springer, Berlin/Heidelberg), pp. 282–291
Metadaten
Titel
Asynchronous Circuits and Their Applications in Hardware Security
verfasst von
Eslam Yahya Tawfik
Waleed Khalil
Copyright-Jahr
2021
DOI
https://doi.org/10.1007/978-3-030-64448-2_19

Neuer Inhalt