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2016 | OriginalPaper | Buchkapitel

Atomic-AES: A Compact Implementation of the AES Encryption/Decryption Core

verfasst von : Subhadeep Banik, Andrey Bogdanov, Francesco Regazzoni

Erschienen in: Progress in Cryptology – INDOCRYPT 2016

Verlag: Springer International Publishing

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Abstract

The implementation of the AES encryption core by Moradi et al. at Eurocrypt 2011 is one of the smallest in terms of gate area. The circuit takes around 2400 gates and operates on an 8 bit datapath. However this is an encryption only core and unable to cater to block cipher modes like CBC and ELmD that require access to both the AES encryption and decryption modules. In this paper we look to investigate whether the basic circuit of Moradi et al. can be tweaked to provide dual functionality of encryption and decryption (ENC/DEC) while keeping the hardware overhead as low as possible. As a result, we report an 8-bit serialized AES circuit that provides the functionality of both encryption and decryption and occupies around 2645 GE with a latency of 226 cycles. This is a substantial improvement over the next smallest AES ENC/DEC circuit (Grain of Sand) by Feldhofer et al. which takes around 3400 gates but has a latency of over 1000 cycles for both the encryption and decryption cycles.

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Fußnoten
1
Another important point to note is that this particular architecture interprets the AES input vectors in a row major fashion i.e. the first four bytes are placed in the first row, the second four bytes in the second row so on. Most AES implementations use a column major ordering.
 
2
One way to achieve this is to use a gated clock which does not present a leading edge during the shiftrow period.
 
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Metadaten
Titel
Atomic-AES: A Compact Implementation of the AES Encryption/Decryption Core
verfasst von
Subhadeep Banik
Andrey Bogdanov
Francesco Regazzoni
Copyright-Jahr
2016
DOI
https://doi.org/10.1007/978-3-319-49890-4_10