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This monograph envisions adaptive low-power multimedia systems covering both the application and processor perspectives. Besides low power consumption, a special focus is on the support for adaptivity which is inevitable when considering the rapid evolution of the multimedia/video standards and high unpredictability due to user interactions, input data, and inclusion of adaptive algorithms in advanced standards. In order to support adaptivity dynamically reconfigurable processors are considered in this monograph. This chapter provides basics and terminology used in video coding and an overview of the H.264 video encoder which is one of the latest video coding standards. Afterwards, a general background of the reconfigurable processors and their low-power infrastructure is discussed in Sect. 2.3 followed by the prominent related work in dynamically reconfigurable processors and low-power approaches for reconfigurable computing. Especially, the RISPP processor [Bau09] is presented in detail as it is used for detailed benchmarking of the processor-level contribution of this monograph (i.e., adaptive low-power processor architecture).
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RGB denotes Red, Green, Blue components of a video frame.
The reason for using YUV space for video coding is its smaller correlation between the color components making the independent encoding of these components easier.
Also called MPEG-4 Part-10 (ISO/IEC 14496-10) or MPEG-4 Advanced Video Coding (AVC).
In this monograph, I8 ´ 8 is not considered as it is not used for the mobile devices. However, the contribution of this monograph is scalable to I8 ´ 8.
For a SKIP Macroblock, encoder does not send any motion and coefficient data and a SKIP Macroblock can be completely reconstructed at the decoder side.
1089 candidate positions per MB for a search window size of 33 ´ 33.
Further details on the Xilinx internal structure and its usage can be found in [Xil07].
Most of the architectures use the Xilinx FPGAs and tools [LBM +06] to prototype partial run-time reconfiguration.
Throughout this paper, a hot spot denotes a computational hot spot that contains compute-intensive application parts (i.e., kernels).
Not necessarily of a particular Custom Instruction, it is rather a representation of the set of Data Paths of two Implementation Versions.
Which Implementation Versions is used to implement a CI is determined at run time, but the composition of individual Implementation Versions are not affected, therefore, they can be prepared at compile time.
FIs and CIs are programmed as inline assembly. The assembler is extended to know about the instruction formats and opcodes of all FIs and CIs occurring in the assembly code.
Bus Macros are used to establish communication between the partially reconfigurable part (i.e., DPC) and the non-reconfigurable part (i.e., BC).
The latch disconnects the Data Path of the DPC from the not-demanded external inputs, thus avoiding unnecessary toggles and reducing the dynamic power consumption of the Data Paths.
- Background and Related Work
- Springer New York
- Chapter 2