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Erschienen in:
Introduction Kapitel lesen Erstes Kapitel lesen

2017 | OriginalPaper | Buchkapitel

3. Background

verfasst von : Felix Winterstein

Erschienen in: Separation Logic for High-level Synthesis

Verlag: Springer International Publishing

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Abstract

Besides the basic high-level synthesis steps, resource allocation, scheduling, binding and the generation of control circuits, a high-level synthesis tool usually performs several optimisation steps and transformations of the input code. This chapter discusses a literature review of existing techniques for parallelisation and memory system optimisations related to high-level synthesis flows. It also introduces separation logic, the theoretical framework leveraged in this thesis.

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Vorheriges Kapitel High-Level Synthesis of Dynamic Data Structures
Nächstes Kapitel Heap Partitioning and Parallelisation
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Metadaten
Titel
Background
verfasst von
Felix Winterstein
Copyright-Jahr
2017
Buch
Separation Logic for High-level Synthesis

Print ISBN: 978-3-319-53221-9

Electronic ISBN: 978-3-319-53222-6

Copyright-Jahr: 2017

DOI
https://doi.org/10.1007/978-3-319-53222-6_3

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