Weitere Kapitel dieses Buchs durch Wischen aufrufen
In this chapter, the adaptive low-power application and processor architectures are benchmarked. The evaluation and analysis of the individual parts of the proposed adaptive low-power application and processor architecture are already presented in Chap. 4 and 5, respectively. The first section will provide benchmarks for different algorithms at the Mode Decision and Motion Estimation levels for realizing adaptive low-power video coding. These algorithms are compared with different state-of-the-art fast and adaptive approaches. This section additionally provides the comparison with the exhaustive Rate Distortion Optimized Mode Decision (RDO-MD) and exhaustive search algorithms to benchmark against the optimal quality as it is typically done by the related work, too. The second section benchmarks the adaptive low-power reconfigurable processor architecture (with energy management scheme) against state-of-the-art reconfigurable processor. The following two different types of dynamically reconfigurable processor architectures are considered for comparison.
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These approaches [Ge04; MM05] are considered for the comparison as they are the closest to the proposed technique in terms of shutdown options for different components of the fabric, thus representing a fair comparison.
Note: the power-shutdown is disabled in case of RISPP_PerfMax, as switched-off DPCs lose their configuration data and this typically degrades the performance, e.g., when the same Data Paths are needed soon afterwards. Comparison with RISPP_PerfMax also demonstrates the performance loss of AEM_FM compared to the peak performance.
The larger leakage power does not necessarily lead to larger leakage energy if the execution time is correspondingly shorter.
- Benchmarks and Results
- Springer New York
- Chapter 7