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Über dieses Buch

This book describes the bottleneck faced soon by designers of traditional CMOS devices, due to device scaling, power and energy consumption, and variability limitations. This book aims at bridging the gap between device technology and architecture/system design. Readers will learn about challenges and opportunities presented by “beyond-CMOS devices” and gain insight into how these might be leveraged to build energy-efficient electronic systems.



Chapter 1. Beyond-Silicon Devices: Considerations for Circuits and Architectures

While the relentless scaling of silicon-based field-effect transistors (FETs) has improved digital system performance for decades, the benefits moving forward are suffering from diminishing returns. How then can digital computing systems meet future energy efficiency requirements, for example, for future Internet-of-Everything (IoE) and abundant-data applications? To answer this outstanding question, a wide range of emerging nanotechnologies are currently being explored to replace silicon as the channel material for future transistors. In particular, carbon nanotube (CNT) FETs (CNFETs) are a highly promising candidate to continue to improve energy efficiency of digital VLSI circuits, as high-performance/energy-efficient CNFETs have been experimentally demonstrated, and larger-scale CNFET circuits and systems integrating millions of CNFETs have been experimentally demonstrated as well. In this chapter, we discuss the benefits of CNFET for VLSI circuits, and describe combined processing and design techniques to transform CNTs from a promising technology into highly energy-efficient digital circuits. Furthermore, CNFETs offer a unique opportunity to realize entirely new three-dimensional (3D) computing architectures, in which multiple layers of CNFET circuits can be densely integrated on top of each other over the same starting substrate, along with layers of memory, truly embodying computation immersed in memory. We provide an overview of the resulting 3D systems, that is, 3D nanosystems, and demonstrate that they offer EDP benefits in the range of 1000× for next-generation abundant-data applications.
Gage Hills, H.-S. Philip Wong, Subhasish Mitra

Chapter 2. Functionality-Enhanced Devices: From Transistors to Circuit-Level Opportunities

Complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have been the fundamental brick for the development of modern micro-electronics since their introduction in the 1970s. Complementary logic gates are based on the use of two kinds of transistors, n- and p-type, having opposite polarity. The fixed polarity of each device is determined during the fabrication process by implantation of dopant atoms, which provide the charge carriers needed for conduction. In contrast to this approach, a new device concept has been introduced, where an intrinsic, non-doped material is used, and additional gate electrodes allow for the selection of the charge carriers. The polarity of the device can thus be dynamically selected at run-time, and other operation modes can be exploited using particular combinations of the gate inputs. This chapter is dedicated to this class of functionality-enhanced devices and covers recent developments in the field, spanning from the basic operation principles of multiple-independent-gate (MIG) FETs to their applications in the creation of highly compact logic gates for beyond-CMOS electronics.
Giovanni V. Resta, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Chapter 3. Heterogeneous Integration of 2D Materials and Devices on a Si Platform

Two-dimensional (2D) materials are atomically thin layered crystals with weak van der Waals interactions in between layers. Their unique electrical and optoelectronic properties and the easiness of their integration with silicon technologies have made 2D materials and devices a very promising and flexible platform for More-than-Moore applications. In this chapter, we discuss some of the opportunities of this heterogeneous integration in next-generation electronic, optoelectronic, and chemical/biological sensing applications.
Amirhasan Nourbakhsh, Lili Yu, Yuxuan Lin, Marek Hempel, Ren-Jye Shiue, Dirk Englund, Tomás Palacios

Chapter 4. Emerging NVM Circuit Techniques and Implementations for Energy-Efficient Systems

This chapter addresses emerging resistive nonvolatile memory (NVM) circuit design techniques and implementations for energy-efficient systems. First we introduce emerging memory technologies, including resistive RAM (ReRAM), phase change memory (PCM), and spin-torque transfer magnetic RAM (STT-MRAM). Next, we examine circuit design challenges for read and write operations, and review some of the advanced circuit techniques. Lastly, we discuss the implementation for energy-efficient systems with nonvolatile logic and nonvolatile SRAM using emerging resistive NVM.
Win-San Khwa, Darsen Lu, Chun-Meng Dou, Meng-Fan Chang

Chapter 5. The Processing-in-Memory Paradigm: Mechanisms to Enable Adoption

Performance improvements from DRAM technology scaling have been lagging behind the improvements from logic technology scaling for many years. As application demand for main memory continues to grow, DRAM-based main memory is increasingly becoming a larger system bottleneck in terms of both performance and energy consumption. A major reason for poor memory performance and energy efficiency is memory’s inability to perform computation. Instead, data stored within DRAM memory must be moved into the CPU before any computation can take place. This data movement is costly, as it requires a high latency and consumes significant energy to transfer the data across the pin-limited memory channel. Moreover, the data moved to the CPU is often not reused, and thus does not benefit from being cached within the CPU, which makes it difficult to amortize the overhead of data movement.
Modern 3D-stacked DRAM architectures provide an opportunity to avoid unnecessary data movement between memory and the CPU. These multi-layer architectures include a logic layer, where compute logic can be integrated underneath multiple layers of DRAM cell arrays (i.e., the memory layers) within the same chip. Architects can take advantage of the logic layer to perform processing-in-memory (PIM), or near-data processing, where some of the computation is moved from the CPU to the logic layer underneath the memory layer. In a PIM architecture, the logic layer within DRAM has access to the high internal bandwidth available within 3D-stacked DRAM (which is much greater than the bandwidth available in the narrow memory channel between DRAM and the CPU). Thus, PIM architectures can effectively free up valuable bandwidth on the bandwidth-limited memory channel while at the same time reducing system energy consumption.
A number of important issues arise when we add compute logic to DRAM. In particular, logic within DRAM does not have low-latency access to common CPU structures that are essential for modern application execution, such as the virtual memory mechanisms, e.g., the translation lookaside buffer (TLB) or the page table walker, and the cache coherence mechanisms, e.g., the coherence directory. To ease the widespread adoption of PIM, we ideally would like to maintain traditional virtual memory abstractions and the shared memory programming model. This requires efficient mechanisms that can provide logic in DRAM with access to virtual memory and cache coherence without having to communicate frequently with the CPU, as off-chip communication between the CPU and DRAM consumes much of the limited bandwidth that PIM aims to avoid using. To this end, we propose and evaluate two general-purpose solutions that can be used by PIM architectures to minimize unnecessary off-chip communication. The first, IMPICA, is an efficient in-memory accelerator for pointer chasing, which can handle address translation entirely within DRAM. The second, LazyPIM, provides coherence support without the need to continually communicate with the CPU. We show that both of these mechanisms provide a significant benefit for a number of important memory-intensive applications, thereby both improving performance and reducing energy consumption.
Saugata Ghose, Kevin Hsieh, Amirali Boroumand, Rachata Ausavarungnirun, Onur Mutlu

Chapter 6. Emerging Steep-Slope Devices and Circuits: Opportunities and Challenges

While continuing the CMOS scaling-down becomes unprecedentedly more challenging than before, intensive exploration on beyond-CMOS nanodevice technologies is an appealing approach to further continue the power scaling-down. This chapter reviews some promising beyond-CMOS emerging transistor technologies, including Tunnel FETs, Ferroelectric FETs, and Hyper-FETs. Circuit design techniques based on these emerging devices are also reviewed to provide insights for future energy-efficient analog and digital signal processing. In addition to the opportunities, this chapter also discusses the challenges of emerging devices in circuit and systems.
Xueqing Li, Moon Seok Kim, Sumitha George, Ahmedullah Aziz, Matthew Jerry, Nikhil Shukla, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan

Chapter 7. Spin-Based Majority Computation

The downscaling of Complementary Metal Oxide Semiconductor (CMOS) devices will come to an end in the following decade. This has accelerated research that explores new device concepts that can help the semiconductor industry move forward, beyond the CMOS roadmap. Such device concepts include spin-based technologies which have a propensity to low-energy operation and non-volatility. More specifically, Spin Wave Devices (SWD) and Spin Torque Majority Gates (STMG) can be used to construct logic circuits that efficiently use a majority gate primitive. This leads to logic optimization that can enable more compact and energy-efficient circuits. In this chapter we describe operating principles and dynamic behavior of SWD and STMG. We present circuit benchmarking and outlook for these two concepts and discuss the action points that will enable them.
Odysseas Zografos, Adrien Vaysset, Bart Sorée, Praveen Raghavan


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