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Dieser Artikel befasst sich mit der Optimierung der Ebit-Kosten in verteilten Quantenschaltkreisen und konzentriert sich auf die Verwendung von binärer Integer-Programmierung (BIP), um Verschränkungsressourcen und nicht-lokale Operationen zu minimieren. Die Autoren stellen einen neuartigen Ansatz vor, der die Modulzuweisung von der Ebit-Verteilung entkoppelt und so eine stabilere und effizientere Lösung ermöglicht. Der Artikel liefert detaillierte Ableitungen und Beweise, die die Wirksamkeit der BIP-Formulierung bei der Reduzierung der Ebit-Kosten für verschiedene Schaltungstypen aufzeigen. Darüber hinaus diskutieren die Autoren die Anwendung ihrer Methode auf strukturierte Schaltkreise wie Quantenfourier-Transformationsschaltkreise (QFT) und unterstreichen die Bedeutung ihres Nachbearbeitungsschritts für robuste Ergebnisse. Die experimentellen Ergebnisse zeigen signifikante Verbesserungen bei der Ebit-Kostenreduzierung, insbesondere für Schaltungen mit höheren Anteilen an nicht-lokalen Gates. Der Artikel schließt mit einer Skizze potenzieller Richtungen für weitere Forschung, einschließlich der Ausnutzung lokaler Gesetzmäßigkeiten und der Erweiterung ganzheitlicher Programmiermodelle, um zusätzliche Systembeschränkungen einzubeziehen.
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Abstract
Modular and networked quantum architectures can scale beyond the qubit count of a single device, but executing a circuit across modules requires implementing non-local two-qubit gates using shared entanglement (ebits) and classical communication, making ebit cost a central resource in distributed execution. The resulting distributed quantum circuit (DQC) problem is combinatorial, motivating prior heuristic approaches such as hypergraph partitioning. In this work, we decouple module allocation from distribution. For a fixed module allocation (i.e., assignment of each qubit to a specific quantum processing unit), we formulate the remaining distribution layer as an exact binary integer programming (BIP). This yields solver optimal distributions for the fixed allocation subproblem and can be used as a post-processing step on top of any existing allocation method. We derive compact BIP formulations for four or more modules and a tighter specialization for three modules. Across a diverse benchmark suite, BIP post-processing reduces ebit cost by up to 20% for random circuits and by more than an order of magnitude for some arithmetic circuits. While the method incurs offline classical overhead, it is amortized when circuits are executed repeatedly.
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1 Introduction
In recent years, the capacity of quantum computing hardware has steadily increased [1‐4]. However, a significant obstacle to realizing the full potential of quantum computing is the limited number of qubits available in a single quantum computer (or module) [5‐8]. To overcome this, distributing a large quantum computation over a network of modules has emerged as a promising approach [9‐13].
The distributed quantum circuit (DQC) problem involves dividing a quantum circuit across multiple modules. A non-local controlled unitary gate between two modules can be realized using only local quantum operations and classical communication if the modules share a Bell state [14‐16], which is referred to as an \(\textit{ebit}\) [17‐20]. Typically, an algorithm used to solve DQC attempts to minimize the ebit cost for circuit execution. Its goal is to map the qubits in the circuit to individual modules and determine how to implement the non-local operations between modules in a way that minimizes the number of required ebits.
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This paper primarily considers homogeneous networks with \(k \ge 3\) modules. In this setting, distributions using a hypergraph partitioning formulation and heuristic solvers proved to be the most effective [19, 20]. However, this approach jointly determines the module allocation and the implementation of non-local gates based on that allocation, even though the former cannot logically depend on the latter. As our main contribution, we observe that exact binary integer programming (BIP) formulations [21‐23] under a fixed module allocation function (i.e., assignment of each qubit to a specific quantum processing unit (QPU)) yield improved ebit costs, demonstrating stability for various types of circuits. First, we present formulations for \(k \ge 4\) modules and then show how it simplifies for \(k = 3\) modules. As a result, our method can be combined with any DQC solver by ignoring its distribution steps and adopting only the module allocation it returns. Our approach further reduces ebit costs for various types of circuits, with significant improvements observed in some structured circuits. This highlights the importance of our post-processing for achieving robust results.
The motivation for using a BIP formulation is that, given a fixed module allocation, selecting migrations (defined in Sect. 2.3) to cover all non-local gates reduces to a discrete subset selection problem with binary decisions. An exact BIP formulation yields (solver) optimal solutions for this fixed module subproblem, enabling a principled post-processing step that can be plugged into any existing method by reusing its module allocation and optimizing only the distribution layer.
The rest of this paper is organized as follows. Section 2 provides an overview of the background and related works. In Sect. 3, we present detailed derivations and proofs of our BIP formulations, along with an explanation of the unique characteristics of distributing quantum Fourier transform (QFT) circuits [14, 24, 25]. Section 4 presents experimental results, which have been validated on various circuits. Finally, Sect. 5 concludes the paper and offers a perspective on future work.
2 Preliminaries
At its core, the objective of this work can be summarized as follows: Given a monolithic quantum circuit C, how can we optimally distribute its constituent gates across k distinct hardware modules while minimizing the overhead of entanglement resources and non-local operations? In the following sections, we transition into the formal definitions of distributed quantum architectures. The concepts introduced in this section are used throughout and will be required to state our BIP formulation in Sect. 3.
Fig. 1
Example network of five QPUs. Every pair of modules shares entanglement resources to facilitate non-local gate operations. This distributed architecture enables large-scale quantum circuits through a combination of local quantum operations and inter-module classical communication
In the context of distributed quantum computing, a module refers to an individual quantum computer that forms part of a larger, interconnected network [20] (represented as a box in Fig. 1). Modern quantum architectures often face scaling limitations where the qubit count of a single device is insufficient for large-scale algorithms. To overcome this, software tools must partition a global circuit into smaller fragments that can be executed across multiple modules, allowing them to function collectively as a single, powerful processor. This distributed execution, however, necessitates sophisticated non-local gate operations and advanced compiler strategies to determine an optimal circuit layout, which amounts to minimizing the entanglement and communication overhead between modules.
As in previous studies, we consider a quantum circuit to be composed only of unary and binary gates [17‐20]. Here, each binary gate is a controlled phase (CP) gate [14]
where \(\mathbb {I}\) denotes the single-qubit identity operator. Any circuit can be transformed into an equivalent circuit in this form, a fact that follows from the universality of the set consisting of all unary gates and the CNOT gate [26].
Distributing an n-qubit quantum circuit involves two steps. First, each qubit must be assigned to a module. Second, non-local gates are identified based on this module allocation, and the optimal method to implement these gates with the least resources is determined. This overall process is referred to as the DQC problem. Typically, a \((k, \epsilon )\)balanced partition is used for module allocation, ensuring that each module contains at most \((1 + \epsilon ) \frac{n}{k}\) qubits [17]. By a reduction from the hypergraph min-cut problem, the DQC problem was shown to be NP-hard [18]. This complexity implies that finding a globally optimal distribution for large-scale circuits is computationally intractable, traditionally necessitating the use of heuristic approaches such as hypergraph partitioning. However, these heuristics often bundle module allocation and ebit distribution together, potentially missing significant resource savings. By decoupling these steps, we can isolate the ebit distribution layer as a subproblem that can be solved via BIP. This allows our method to refine heuristic-based pipelines, providing a better solution for a given module allocation under which a standard heuristic alone would settle for suboptimal resource costs.
Fig. 2
Implementation of a non-local gate. Module A contains qubits (a, e) and Module B contains qubits \((e^\prime ,b)\). The controlled-U gate \(CU_{a\rightarrow b}\) with control a and target b can be realized using only local operations and classical communication at the cost of a single ebit \(|\Phi ^+\rangle _{ee^\prime }\) shared between A and B
between two modules A and B, which is a maximally entangled bipartite state. In the context of DQC, such states are referred to as ebits. Figure 2 shows how to implement a non-local controlled unitary gate with a single control qubit a and a single target qubit b at the cost of a single ebit (for a complete validation of this protocol, see Appendix A). The steps before (after) the controlled unitary gate constitute a cat-entanglement (cat-disentanglement) process. The former creates a linked copy of a in module B, and the latter effectively reverses this process. After cat disentanglement, operations such as \(CP(\theta )_{a\rightarrow b}\) can be successfully implemented. In practice, the end-to-end fidelity and runtime of this ebit-assisted cat (dis)entanglement are currently limited by the mid-circuit measurements and real-time feedforward, but existing demonstrations already mitigate part of this overhead to make non-local operations more robust [27, 28].
Suppose we create linked copies of a qubit q at modules other than the one including q. This cat-entanglement operation (i) commutes with CP gates acting on q and (ii) generally does not commute with arbitrary unary gates acting on q (see Appendices B and C). The first property allows us to restrict the creation of a linked copy of q in any module to occur immediately after one of the unary operations on q or at time 0, assuming that the circuit is compiled exclusively with CP gates and unary gates. The second property implies that in general, all linked copies of q in other modules must be reintegrated into q before a unary gate acts on q.
2.3 Problem formulation
To formally address the distribution of gates across a modular architecture, we first define the structure of the input quantum circuit C. Our goal is to transform this monolithic circuit into a partitioned representation that can be mapped onto k hardware modules. To achieve this, we model the circuit as a collection of discrete gate events in space and time, categorized by their qubit dependencies.
Specifically, we represent a quantum circuit acting on a set of n qubits \(Q = \{ q_i \}_{i = 1}^{n}\) as a finite set \(C = U \cup B\), where
$$\begin{aligned} U = \bigcup _{i=1}^{n} \left\{ (q_i, t) \mid t \in T^{(i)} \subset \mathbb {N} \right\} \end{aligned}$$
is a set of unary gates and
$$\begin{aligned} B = \bigcup _{1 \le i < j \le n} \left\{ (\{q_i, q_j\}, t) \mid t \in T^{(\{i, j\})} \subset \mathbb {N} \right\} \end{aligned}$$
is a set of non-local binary gates. As is clear from the notation, \((q_i, t)\) represents a unary gate acting on \(q_i\) at time t and \((\{q_i, q_j\}, t)\) represents a binary gate acting on \(\{ q_i, q_j \}\) at time t. Without loss of generality, it is assumed that all \(T^{(i)}\) and \(T^{(\{i, j\})}\) are mutually exclusive.
In what follows, we assume that there are \(k \ge 3\) modules in total, i.e., \(P = \{ p_1, p_2, \cdots , p_k \}\), and that we are given a module allocation function \(\pi : Q \rightarrow P\). This implies that \(\pi (q_i) \ne \pi (q_j)\) for all \((\{q_i, q_j\}, t) \in B\). The concept of migration was first defined in Ref. [17]. Intuitively, a migration does not physically move a qubit between modules. Rather, it denotes a temporary, protocol-level operation in which the quantum information of a logical qubit is made available at another module so that subsequent CP gates that would otherwise be non-local can be executed locally at that module. Technically, a migration represents the cat-entanglement operation in Sect. 2.2. It also implicitly assumes that cat disentanglements are performed whenever necessary.
Definition 1
(Migration [17]) A migration is a triple (q, p, t), which translates to creating a linked copy of q in module p at time t. The set of all candidate migrations is defined as
$$\begin{aligned} M \equiv \bigcup _{i = 1}^{n} \bigcup _{p \in P \setminus \{ \pi (q_i) \}} \left\{ (q_i, p, t) \mid t \in \{0\} \cup T^{(i)} \right\} . \end{aligned}$$
For a non-local CP gate, home coverage restricts us to migrating one endpoint qubit to the home module of the other endpoint, so that the gate can be executed where one of its qubits already belongs. In contrast, joint coverage allows two migrations executing the gate at a third module by migrating both endpoint qubits there. This greatly enlarges the combinatorial choices because it couples the selection decisions for the two qubits. Formally, we have the following definitions.
Definition 2
(Home coverage [17]) For a non-local CP gate \(g = (\{ q_i, q_j \}, t^*)\), we say that a migration (q, p, t) home covers g if one of the following conditions holds, thereby enabling the execution of g.
(Joint coverage [17]) For a non-local CP gate \(g = (\{ q_i, q_j \}, t^*)\), we say that a pair of migrations \(\{ (q_{i'}, p, t), (q_{j'}, p, t') \}\) joint covers g if the following condition holds, thereby enabling the execution of g.
Given \(\pi \), the problem of finding the minimum subset of M that covers all gates in B following Definition 2 is called migration selection under home coverage (MS-HC). If we further allow joint coverage in Definition 3, then the problem is called migration selection under general coverage (MS-GC). We remark that MS-HC can be viewed as a set cover instance with highly restricted structure, and an optimal polynomial-time algorithm for MS-HC given \(\pi \) has been identified. On the other hand, joint coverage significantly expands the search space, and MS-GC is conjectured to be NP-hard. A heuristic for MS-GC was proposed, which greedily adds a set of migrations at each iteration based on some criterion [17].
Importantly, this work does not claim a polynomial-time algorithm for MS-GC. Instead, our contribution is an exact BIP formulation for MS-GC under a fixed \(\pi \), which we use as a post-processing step. Starting from any candidate allocation \(\pi \) (e.g., produced by a heuristic allocator), we solve the corresponding fixed-\(\pi \) BIP to obtain an ebit distribution for that allocation. This improves the ebit cost without changing the module allocation.
2.4 Hypergraph partitioning formulation
Fig. 3
a Example distributed circuit for \(k=3\) modules. Wires with the same color belong to the same module. The labels 1, 1, 2, 2, 3, 3 on the left are the module indices of the six logical qubits (each module contains two qubits). White squares represent single-qubit gates and the symbols \(\alpha ,\beta ,\gamma ,\delta \) denote two-qubit gates (with repeated \(\delta \)-blocks). Downward arrows indicate migrations (here, to module 3). b Hypergraph representation of the same instance, with qubit vertices \(q_1,\ldots ,q_6\) and gate vertices \(\alpha ,\beta ,\gamma ,\delta \). Qubit vertex colors indicate their home modules, whereas gate vertex colors indicate the modules where the corresponding gates are executed
Our BIP post-processing requires a module allocation \(\pi \) as input. In practice, we can obtain \(\pi \) from existing allocation heuristics and in particular from the hypergraph partitioning formulation of circuit distribution [18], which has achieved the best performance for \(k \ge 3\) [19, 20]. We briefly summarize this construction here for completeness. Readers interested only in the post-processing formulation may skip to Sect. 3.
Given a circuit C, the corresponding hypergraph is constructed as follows. First, a node is added for each binary gate and for each qubit. Second, for each qubit \(q_i\) and time interval \(I = (t, t')\) such that the following conditions are satisfied, a hyperedge that connects \(q_i\) and all the binary gates that act on \(q_i\) within I is added, if such gate exists:
Fig. 3 shows an example circuit distributed by this method. The coverage of the gate \(\alpha \) is a joint coverage, and the coverages of the gates \(\beta \) and \(\gamma \) are home coverages.
3 Algorithmic improvements and examples
The full DQC pipeline consists of two layers: a module allocation step that fixes \(\pi :Q\rightarrow P\), followed by a distribution step that selects migrations to cover all non-local gates. The latter step is precisely MS-GC under a fixed \(\pi \), and existing approaches rely on heuristics because MS-GC is conjectured to be NP-hard. Our goal in this section is therefore not to obtain a new allocator, but to provide a post-processing method that, for any given \(\pi \), computes the set of migrations for that allocation. To this end, we formulate fixed-\(\pi \) MS-GC as a BIP, which serves as a drop-in improvement layer on top of any module allocation heuristic by optimizing only the migration-selection layer.
We begin by describing a BIP formulation of MS-GC for \(k \ge 4\). A more efficient formulation for \(k = 3\) is described in Sect. 3.2.
In simpler terms, \(M^{(1, (\{q_i, q_j\}, t))}\) denotes a pair of migrations, where each migration in the pair migrates one of the qubits to the other qubit’s module; \(M^{(2, (\{q_i, q_j\}, t))}\) denotes a set of pairs of migrations, where each pair in the set comprises migrations that migrate both qubits to a module that contains neither of them. We proceed to define the following unions:
To express the BIP compactly, we fix an arbitrary but consistent ordering of each set and treat it as an indexed list. This allows us to introduce decision variables and constraints using subscripts without repeatedly naming individual migrations. Specifically, for any set S we employ the notation
$$\begin{aligned} \forall 1 \le i \le |S|, \quad S_i \in S \quad \text {and} \quad S.\text {idx}(S_i) = i. \end{aligned}$$
Each row of A contains \(2 + (k - 2) = k\) nonzero elements. Let \(x \in \{0, 1\}^{|\tilde{M}|}\) represent the set of all selected migrations and pairs of migrations, which is a subset of \(\tilde{M}\). To ensure that x is a valid representation, we impose the constraint that if a pair of migrations is selected, then each migration in the pair must also be selected. For each pair of migrations \({\textbf {m}} \in M^{(2)}\), we add a constraint to the vector x as \(e^{({\textbf {m}})\top } x \ge 0\), where
and \(e_i\) denotes the ith standard unit vector in \(|\tilde{M}|\) dimensions.
Let \({\varvec{0}}_d\) and \({\varvec{1}}_d\) denote the all-zeros vector and the all-ones vector in d dimensions, respectively. Then the objective is defined as
and A is defined as in Eq. (3) (see Algorithm 1). Algorithm 1 obtains the minimizer in Step 26 by passing the BIP instance to a standard mixed integer solver (we use Gurobi [29]), which searches over \(x\in \mathbb {B}^{|\tilde{M}|}\). Therefore, the returned x specifies an MS-GC solution for the given \(\pi \), and its objective value equals the ebit cost achievable with that solution.
To summarize, we enforce that every gate is covered by selecting at least one admissible covering option (either a home coverage or a joint coverage), while guaranteeing logical consistency by preventing the selection of a joint coverage unless its constituent migrations are also selected. The objective in Eq. (4) then counts the number of selected single migrations (i.e., the ebit cost), so minimizing it yields the minimum-cost feasible cover under general coverage for the fixed allocation \(\pi \). Formally, we explain the validity of this formulation through the following observation.
for some \({\textbf {m}} \in M^{(2)}\). Then \(\hat{x}^{({\textbf {m}})} \equiv \hat{x} + e_{\tilde{M}.\text {idx}({\textbf {m}})}\) is also an optimal solution because
where \(g = (\{ q_i, q_j \}, t)\) and \(p \in P {\setminus } \{ \pi (q_i), \pi (q_j) \}\) is unique. Before we describe the objective function, we remark that the optimization is with respect to \(x \in \mathbb {B}^{|M^{(1)}|}\) instead of \(x \in \mathbb {B}^{|M|}\). We justify this reduction of variables through the following lemma.
Lemma 1
If \(k = 3\), the power set \(2^{M^{(1)}}\) includes an optimal choice of migrations.
Proof
We prove by contradiction. Let \(P = \{p_1, p_2, p_3\}\) and \(\pi (q_i) = p_1\). Suppose \(m = (q_i, p_2, t) \notin M^{(1)}\) for some \(m \in M\) is strictly necessary. By the definition of \(M^{(1)}\), there is no gate \((\{q_i, q_j\}, t')\) such that \(\pi (q_j) = p_2\) and \(f(i, t') = t\). This means that the non-local binary gates that m can cover (by itself or in a pair with another migration) must be in the form of \((\{q_i, q_j\}, t')\), where \(\pi (q_j) = p_3\) and \(f(i, t') = t\) (and in fact, m cannot cover one of these gates by itself because it migrates \(q_i\) in \(p_1\) to \(p_2\) while the gate acts on a qubit in \(p_3\); it must be paired with a migration that sends \(q_j\) to \(p_2\)). Since we assumed that m is strictly necessary, there must exist at least one such gate. Meanwhile, notice that those gates are all covered by the single migration \(m' = (q_i, p_3, t) \in M^{(1)}\). Therefore, replacing m with \(m'\) does not increase the number of selected migrations without introducing any uncovered gates, which implies that any migration \(m \notin M^{(1)}\) is not strictly necessary; each of them can be replaced by some \(m' \in M^{(1)}\). \(\square \)
Fig. 4
Illustration of why \(k=3\) admits a reduced formulation (Lemma 1) while \(k\ge 4\) does not. Gray boxes show module indices (each module contains a single qubit), and arrows denote migrations. a\(k=3\): Removing the red migration makes the red gate uncovered, but it can still be covered by the single blue migration because the blue migration (which is an element of \(M^{(1)}\)) moves the same qubit to the other endpoint’s home module. This reflects that migrations outside \(M^{(1)}\) can be replaced without increasing cost. b\(k=4\): The circuit includes an additional set of gates, and removing the red migration leaves the red gates uncovered in a way that cannot be repaired by any single migration. This contrast explains why we can restrict migrations to \(M^{(1)}\) for \(k=3\), but not for \(k\ge 4\)
Figure 4 provides an example circuit to visualize Lemma 1, as well as a circuit with \(k = 4\) to which the lemma does not apply. The contrast stems from the fact that when \(k=3\) there is only one “third” module besides the two endpoint modules of any migration, whereas for \(k\ge 4\) there are multiple possible third modules.
The objective is defined as
$$\begin{aligned} \text {minimize} \quad&{\varvec{1}}_{|M^{(1)}|}^{\top } x \nonumber \\ \text {subject to} \quad&A x \ge 2 \cdot {\varvec{1}}_{|B|}, \end{aligned}$$
(10)
where A is defined as in Eq. (9). We explain the validity of this formulation through the following observation.
Observation 2
A solution of Eq. (10) is an optimal solution of MS-GC for \(k = 3\).
Proof
By the definition of A, it is clear that \(A_{i,:} x \ge 2\) if and only if a non-empty subset of \(\left\{ M^{(1, B_i)}_1, M^{(1, B_i)}_2, M^{(2, B_i)}_1\right\} \) is selected, where \(A_{i,:}\) denotes the ith row of A. \(\square \)
Note that this is not a valid formulation for \(k \ge 4\). For a gate \(g = (\{q_i, q_j\}, t)\), consider two modules \(p, p' \in P {\setminus } \{ \pi (q_i),\pi (q_j) \}\) such that \(p \ne p'\). We cannot distinguish the selection of the pair
which does not cover g. In general, it is impossible for four positive “rewards” \(r_1\), \(r_2\), \(r_3\) and \(r_4\) to satisfy the conditions where \(r_1 + r_2\) and \(r_3 + r_4\) are greater than or equal to a threshold \(\text {th}\), while \(r_1 + r_3\), \(r_1 + r_4\), \(r_2 + r_3\) and \(r_2 + r_4\) are all less than \(\text {th}\).
Remark 1
The BIP formulations in Eqs. (4) and (10) are naturally generalized to heterogeneous settings, where the communication cost between each pair of modules is not constant. We simply replace \(\left[ {\varvec{1}}_{|M|}^{\top } {\varvec{0}}_{|M^{(2)}|}^{\top }\right] \) and \({\varvec{1}}_{|M^{(1)}|}^{\top }\) with the vectors that represent the cost function.
3.3 Illustrative example
Fig. 5
a Distribution found by a hypergraph partitioner and b BIP post-processing. Numbers denote qubit indices and wires of the same color are assigned to the same module. Arrows indicate migrations. The ebit cost drops from 4 in a to 3 in b. The fact that the hypergraph partitioner is suboptimal even on this tiny instance motivates our BIP post-processing step
Selecting the module allocation together with the corresponding migrations and ebit distribution is combinatorially difficult. Even for small circuits, the hypergraph partitioner can return suboptimal distributions, and our BIP post-processing can reduce the ebit cost. For example, Fig. 5 compares the distribution produced by the hypergraph partitioning approach in Sect. 2.4 with the distribution after BIP post-processing: The ebit cost drops from 4 to 3.
3.4 Problem size of the BIP formulations
Assuming that there are at least O(n) gates in C, the number of binary variables is
In the previous sections, we focused on the migration-selection layer. That is, for a given module allocation \(\pi \), we showed that MS-GC can be formulated as a BIP. We also illustrated that the distribution produced by hypergraph partitioning [18] can be suboptimal.
In this section, we turn to the module allocation layer itself and discuss a structured case where \(\pi \) can be chosen in a principled way. We focus on QFT because it is a core subroutine used in many quantum algorithms, so improving its distributed implementation is valuable in its own right. Moreover, assuming a balanced distribution, QFT exhibits additional structure that makes identifying an optimal \(\pi \) tractable in the (restricted) MS-HC setting.
Fig. 6
A monolithic 6-qubit QFT circuit (SWAP gates omitted). After fixing a module allocation, we remove gates that are local to each module and optimize only the remaining non-local operations
Note that we can omit the final SWAP gates and interpret the qubits in reverse order [25, 30]. In the subsequent diagrams, we replace each H/\(CP(2 \pi / 2^k)\) gate with a general unary/CP gate symbol.
Definition 4
A (k, m)-balanced distribution of QFT is a distribution of the QFT circuit for \(n = km\) qubits, where k and m denote the number of modules and the number of qubits per module, respectively.
It turns out that we can derive an optimal solution for any (k, m)-balanced distribution of QFT, assuming MS-HC. The resulting ebit cost coincides with that derived independently by [31]. However, we strengthen their result by establishing that this cost attains a matching lower bound, thereby proving the optimality of the scheme in the MS-HC setting. Furthermore, the module allocation introduced in the proof will also be reused in the MS-GC setting.
Remark 2
While we omit the final SWAP gates in our QFT distribution, [31] achieves the same ebit cost even when these operations are explicitly included. They accomplish this by employing qubit routing, but such techniques fall outside the scope of our specific model (i.e., MS-GC under fixed \(\pi \)). More importantly, as noted in [32], these final SWAP gates can be omitted without introducing overhead in downstream processing. This is because the SWAP gates merely permute the logical qubits, and their effect can be compensated for through simple qubit reindexing.
In QFT, each qubit has exactly one unary gate and then interacts via CP with every other qubit, so under MS-HC the natural migration time is immediately after that unary gate. In a (k, m)-balanced allocation, migrating a qubit into a module can cover at most m gates between that qubit and the m qubits in the destination module, giving a tight lower bound on the number of migrations. Formally, we have the following lemma.
Lemma 2
The minimum ebit cost for a (k, m)-balanced distribution of the QFT circuit for \(n = km\) qubits with MS-HC is \(m \left( {\begin{array}{c}k\\ 2\end{array}}\right) \).
Proof
We provide a simple constructive proof. The QFT circuit for \(n = km\) qubits can be fully described by the sets
because the circuit includes only one unary gate per qubit and one binary gate per pair of qubits. That is, \(t_{q_i}\) and \(t_{\{q_i, q_j\}}\) are uniquely defined. Assume that the qubits and gates are arranged in the conventional order as shown in Fig. 6 and let \(\pi \) be a balanced module allocator function, i.e.,
$$\begin{aligned} |\{ i | \pi (q_i) = p_{\kappa } \}| = m, \quad \forall \kappa \in \{ 1, 2, \cdots , k \}. \end{aligned}$$
Consider a migration (q, p, t) where \(\pi (q) \ne p\), and let S be the set of non-local binary gates that can be covered by this migration. Since we assume MS-HC, S is a subset of
Now take \(\pi = \pi ^*\), where the canonical partition\(\pi ^*\) is defined as
$$\begin{aligned} \pi ^*(q_i) = p_{\lceil i / m \rceil }. \end{aligned}$$
(12)
Then the set of all non-local binary gates is
$$\begin{aligned} B = \bigcup _{i = 1}^{(k - 1)m} \bigcup _{\kappa = \lceil i / m \rceil + 1}^{k} \Big \{ \left( \{q_i, q_j\}, t_{\{q_i, q_j\}}\right) \mid \lceil j / m \rceil = \kappa \Big \} \end{aligned}$$
(13)
and the circuit to distribute is \(C = U \cup B\). But each \(\left( \{q_i, q_j\}, t_{\{q_i, q_j\}} \right) \) in Eq. (13) is covered by
$$\begin{aligned} \left( q_i, p_{\lceil j / m \rceil }, f\left( i, t_{\{q_i, q_j\}}\right) = t_{q_i} \right) , \end{aligned}$$
and it follows that the set
$$\begin{aligned} \left\{ \left( q_i, p_{\kappa }, t_{q_i}\right) \mid \lceil i / m \rceil < \kappa \le k \right\} \end{aligned}$$
covers all gates in B with ebit cost \(k(k - 1)m / 2\), which achieves its lower bound Eq. (11). \(\square \)
Fig. 7
a A 6-qubit QFT circuit. b–d Circuit C, MS-HC and MS-GC for module allocation “112233.” e–g Circuit C, MS-HC and MS-GC for module allocation “122331.” Both c and f involve 6 migrations, which is optimal for MS-HC. However, d involves 4 migrations while g involves 5 migrations for MS-GC
Module allocations and ebit costs found by BIP for (3, 2)-balanced distributions of QFT
\(\pi \)
ebit cost
\(\pi \)
ebit cost
112233
4
112323
5
112332
5
121233
5
121323
6
121332
6
122133
5
123123
6
123132
6
122313
6
123213
6
123312
6
122331
5
123231
6
123321
6
–
–
Fig. 8
Histograms of MS-GC ebit cost for (k, m)-balanced distributions of QFT, computed by enumerating all balanced module allocations for the indicated (k, m) and solving the associated BIP. The bar including the canonical partition \(\pi ^*\) is highlighted in orange. In both cases, \(\pi ^*\) attains the minimum MS-GC ebit cost (after BIP) among all balanced allocations, supporting our use of \(\pi ^*\) as the default module allocation for MS-GC
Note that \(\pi ^*\) in Lemma 2 is not the only optimal module allocation for MS-HC (see Fig. 7). However, for \((k, m) = (3, 2)\), it is highly likely that \(\pi ^*\)is the only optimal module allocation for MS-GC (see Table 2). We also ran exhaustive experiments to find the optimal allocations among all balanced allocations for \((k, m) = (4, 2)\) and \((k, m) = (3, 3)\) (see Fig. 8). In both cases, the canonical partitions \(\pi ^*\) were optimal for MS-GC (assuming that the BIP solver found optimal solutions for these small examples). That is, distributing a QFT circuit by solving the BIP associated with \(\pi ^*\) is expected to yield the lowest ebit cost we can hope for. Indeed, we observe that this heuristic proves effective (see Sect. 4.2.1).
Remark 3
One might be tempted to extend this idea beyond QFT by (i) choosing \(\pi \) to be optimal for MS-HC and (ii) applying our BIP post-processing to solve MS-GC under that fixed \(\pi \). In general circuits, however, Step (i) is itself a non-trivial combinatorial problem. Unlike QFT, we do not currently have a generic way to certify an optimal module allocation \(\pi \) even under MS-HC, and moreover, an allocation that is optimal for MS-HC need not be optimal for MS-GC. That said, there may be additional circuit families with exploitable structure where an allocation strategy can be characterized analytically or with lightweight combinatorial methods. Natural candidates include state preparation circuits for highly symmetric target states (e.g., GHZ- and W-type constructions), as well as phase-estimation-type circuits, which contain (inverse) QFT as a subroutine. Identifying such structured classes and deriving allocation rules or provable bounds for them (and then combining these with our BIP post-processing) is an interesting direction for future work.
4 Experimental results
Table 3
Summary of the ebit cost savings achieved by BIP post-processing on top of the hypergraph partitioning baseline (HP). For each benchmark family, we report the maximum and minimum percentage reduction in total ebit cost over all tested configurations
Experiment
Ebit cost reduction (%)
Max.
Min.
CZ fraction-10%
1.05
0.00
CZ fraction-30%
1.56
0.00
CZ fraction-50%
3.33
0.63
CZ fraction-70%
6.77
0.48
CZ fraction-90%
19.6
2.99
Quantum Volume
0.86
0.00
QFT
23.1
0.00
DraperQFTAdder
30.4
0.00
RGQFTMultiplier
95.8
0.00
AND
84.4
0.00
InnerProduct
85.7
0.00
The same algorithm and configuration described in Ref. [20] were used for hypergraph partitioning. For the BIP solver, we used Gurobi 11.0.0 with a Named-User Academic License [29]. It is based on the branch-and-bound paradigm for discrete optimization problems [33, 34]. Table 3 outlines the types of circuits considered in our experiments and summarizes the results by reporting the maximum and minimum ebit cost reduction (in %) across all tested configurations for each family. Full results for every parameter setting are deferred to Appendix D. Notably, the minimum reduction is nonnegative in all cases, i.e., the BIP post-processing never produces a worse ebit cost than the HP baseline in any run.
Remark 4
Our BIP post-processing is performed during offline distribution and therefore adds classical runtime compared to a baseline solver. However, since the goal is to reduce execution time ebit consumption, this overhead is often amortized when a distributed circuit is run many times. In such cases, the onetime post-processing overhead may be outweighed by the repeated savings in ebit cost during execution. Moreover, our method reduces MS-GC to a BIP and then delegates optimization to a standard solver (Gurobi). In the current implementation, the largest instances solved in our environment are around \(n=50\), \(k=8\). The current scalability ceiling is primarily driven by solver capability on these instances. We plan to extend this regime by exploiting circuit-level local regularities to eliminate redundant variables and constraints and thereby accelerate the optimization, while leaving improvements to general-purpose BIP technology outside the scope of this manuscript.
In what follows, we describe the experimental circuit families and their structures in detail. These benchmarks are largely divided into two categories: families of random circuits and families of structured arithmetic circuits. For each family, we provide a representative circuit diagram.
Given parameters (n, d, p), an n-qubit CZ fraction circuit is generated as described in Algorithm 3 [17]. Figure 9 shows an example CZ fraction circuit. Table 3 shows that as the CZ fraction increases from 10% to 90%, the maximum ebit saving achieved by the BIP post-processing grows. Ebit costs for distributing random CZ fraction circuits are shown in Fig. 16 in Appendix D.1.
Given parameters (n, d), an n-qubit quantum volume circuit is generated as described in Algorithm 4 [35]. Figure 10 (right) shows an example quantum volume circuit. Ebit costs for distributing random quantum volume circuits are shown in Fig. 17 in Appendix D.2.
4.2 Arithmetic circuits
4.2.1 QFT circuits
Ebit costs for distributing QFT circuits are shown in Fig. 18 in Appendix D.3. We remark that replacing \(\pi \) (found by a hypergraph partitioner) with \(\pi ^*\) defined in Eq. (12) improved the ebit cost in every single run of the BIP solver. In this regard, we conjecture that for the distribution of QFT circuits, \(\pi ^*\) is not only the optimal module allocation function for MS-HC but also for MS-GC.
4.2.2 DraperQFTAdder
Fig. 11
a Example DraperQFTAdder circuit that performs in-place addition (modulo \(2^2\)) on two 2-qubit registers. b Circuit representation of Eq. (14). c Equivalent circuit obtained by applying Eq. (14)
The DraperQFTAdder is a quantum circuit that leverages QFT to perform addition [36]. Before distribution, we perform a minor optimization on this circuit. Consider the identity
where the subscripts denote qubit indices (see Appendix D.4). The right-hand side appears many times in DraperQFTAdder circuits (Fig. 11). Since SWAP gates require binary gates to implement, we replace the right-hand side of Eq. (14) with the left-hand side. Ebit costs for distributing DraperQFTAdder circuits are shown in Fig. 19 in Appendix D.4.
4.2.3 RGQFTMultiplier
The RGQFTMultiplier is a quantum circuit that leverages QFT to perform multiplication [25]. It stores the product of two \(n'\)-bit inputs out of place. By default, the output register has \(2 n'\) qubits, resulting in a total of \(4 n'\) qubits (Fig. 12).
Ebit costs for distributing RGQFTMultiplier circuits are shown in Fig. 20 in Appendix D.5. Surprisingly, the hypergraph partitioner alone returns extremely inefficient distributions in many cases, and BIP post-processing reduces the ebit costs significantly.
4.3 Boolean logic circuits
The hypergraph partitioning approach performs well for random circuits but sometimes fails to yield good solutions for circuits with fixed structures, as observed in the case of RGQFTMultiplier. Unfortunately, we have yet to identify the reasons behind this failure.
The BIP post-processing based on a given module allocation function (found by any means) enhances stability. We present two additional examples of Boolean logic circuits: the AND circuit and the InnerProduct circuit. Even for small circuit size parameters, the impact of BIP post-processing is significant.
Fig. 12
Example RGQFTMultiplier circuit that computes the product of two bits (\(n' = 1\))
The AND circuit implements the logical AND operation on a number of qubits, i.e., it is a multi-controlled-X gate (Fig. 13a). Ebit costs for distributing AND circuits are shown in Fig. 21 in Appendix D.6.
4.3.2 InnerProduct circuits
InnerProduct is a 2n-qubit Boolean function that computes the inner product of two n-qubit vectors over \(F_2\) (Fig. 13b):
Ebit costs for distributing InnerProduct circuits are shown in Fig. 22 in Appendix D.7.
5 Conclusion and outlook
We proposed exact BIP formulations for the DQC problem. Given a fixed module allocation function, we optimize the remaining migration-selection layer to minimize ebit cost. This decoupling turns the fixed allocation subproblem into a step that can be used as post-processing on top of any allocation method, including hypergraph partitioning. We further derived a tighter specialization for the three-module case, leveraging the fact that it admits a reduced migration search space.
Our experiments indicate that BIP post-processing is a reliable choice for distributions obtained from heuristic allocators. Concretely, we observed reductions of up to 20% for random circuits, and in several structured arithmetic benchmarks, the reduction exceeded an order of magnitude. We also found that the magnitude of improvement depends on circuit structure. For instance, circuits with higher fractions of non-local gates tend to admit larger savings.
The BIP is performed offline during compilation and therefore introduces additional classical runtime, but this overhead can be amortized when the same distributed circuit is executed arbitrarily many times. In this regime, even moderate reductions in ebit cost translate directly into recurring savings in entanglement consumption and classical communication overhead at execution time.
Several directions can further improve scalability and broaden applicability. First, many practical circuits exhibit local regularities (e.g., repeated gate motifs or restricted interaction patterns). Exploiting such structure to eliminate redundant variables and constraints could substantially speed up the optimization. Second, while we highlighted quantum Fourier transform as a structured case where allocation admits principled choices, there may be other structured families where the optimal allocation can be nicely characterized. Combining such allocation rules with BIP post-processing is a promising avenue. Finally, it would be valuable to extend integer programming models beyond the cat-entanglement-based protocol and to incorporate additional system constraints such as restricted inter-module connectivity or heterogeneous link costs [37].
Acknowledgements
This work is in part supported by the National Research Foundation of Korea (NRF, RS-2024-00451435 (20%), RS-2024-00413957 (40%)), Institute of Information & Communications Technology Planning & Evaluation (IITP, 2021-0-01059 (40%)), grant funded by the Ministry of Science and ICT (MSIT), Institute of New Media and Communications (INMAC), and the Brain Korea 21 FOUR program of the Education and Research Program for Future ICT Pioneers.
Declarations
Conflict of interest
The authors declare no Conflict of interest.
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Implementing non-local controlled unitary gate using a shared Bell pair
This section details the underlying mechanics of Fig. 2. Let \(a,e,e',b\) be single-qubit registers. Let U be an arbitrary single-qubit unitary acting on b. We assume the input on ab is an arbitrary pure state
Step 2 (measureeand conditionally correct\(e'\)). Measure e in the computational basis, obtaining outcome \(m\in \{0,1\}\). If \(m=0\), the (unnormalized) post-measurement state on \(a,e',b\) is
Now measure \(e'\) in the computational basis, obtaining outcome \(n\in \{0,1\}\). Conditioned on n, the (unnormalized) post-measurement state on ab is:
Step 5 (applyZonaif\(n=1\)). If \(n=1\), apply Z on a. Since \(Z\vert 0\rangle =\vert 0\rangle \) and \(Z\vert 1\rangle =-\vert 1\rangle \), this removes the relative minus sign in Eq. (A4), giving
BIP improvements observed in CZ fraction circuits. Here, n is the number of qubits, d is the circuit depth, and k is the number of modules. The reduction in ebit cost generally increases with higher CZ fractions, since they correspond to more difficult DQC instances
This section provides the full ebit cost plots for all benchmark families in Sect. 4. Additionally, the execution time for each typical BIP instance is shown as a line plot overlaid on the corresponding bars.
CZ fraction circuits
Quantum Volume circuits
Fig. 17
BIP improvements observed in quantum volume circuits. Here, n is the number of qubits and k is the number of modules. The reduction in ebit cost is relatively marginal for these circuits. This is because as mentioned in [20], rewriting a given quantum volume circuit such that all non-unary gates are CP gates makes the fraction of binary gates quite low. Similar to the results for circuits with low \(CZ\_\text {percent}\) shown in Fig. 16, little improvement is expected
BIP and/or \(\pi ^*\) improvements observed in QFT circuits. Here, k is the number of modules and m is the number of qubits per module. Applying BIP to \(\pi ^*\) consistently yields better results than applying it to an HP-based allocation. This demonstrates that the current HP is suboptimal not only in how it selects migrations but also in the module allocations it produces
BIP improvements observed in RGQFTMultiplier circuits. Here, n is the number of qubits and k is the number of modules. In many configurations, our BIP post-processing achieves significant ebit savings compared to HP
BIP improvements observed in AND circuits. Here, n is the number of qubits and k is the number of modules. In many configurations, our BIP post-processing achieves significant ebit savings compared to HP
BIP improvements observed in InnerProduct circuits. Here, n is the number of qubits and k is the number of modules. Empty bars indicate zero ebit cost. In many configurations, our BIP post-processing achieves significant ebit savings compared to HP
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