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Over the past 10 years, the source of the critical signal delays has undergone a major transition. With the scaling of active device feature sizes into the deep sub-micron regime, the on-chip interconnect has become the primary bottleneck in signal flow within high complexity, high speed integrated circuits (ICs).The smaller feature size in DSM technology nodes reduces the delay of the active devices, however, the effect on delay due to the passive interconnects has increased rapidly, as described by the 2005 International Technology Roadmap for Semiconductors (lTRS) . The transition from an IC dominated by gate delays for feature sizes greater than 250 μm to where the interconnects are the primary source of delay is graphically illustrated in Fig. 3.1. As noted in the figure, the disparity between the relative delay of the interconnect and active devices is exacerbated in each successive technology node. The local wire delay decreases with feature size due to a reduction in the distance among the active devices. Special attention must, however, be placed on the global lines, since the overall speed of current ICs is most often limited by the long distance global interconnects.
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- Buffer Insertion as a Solution to Interconnect Issues
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- Chapter 3