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2021 | OriginalPaper | Buchkapitel

7. CAD for Side-Channel Leakage Assessment

verfasst von : Adib Nahiyan, Miao (Tony) He, Jungmin Park, Mark Tehranipoor

Erschienen in: Emerging Topics in Hardware Security

Verlag: Springer International Publishing

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Abstract

Power side-channel attacks (SCAs) have been proven to be effective at extracting secret keys from hardware implementations of cryptographic algorithms. Therefore, it is imperative to evaluate if the hardware is vulnerable to SCAs during its design and validation stages. Ideally, this validation should be performed as early as the pre-silicon stage. In this chapter, we present some existing techniques for PSCL assessment and discuss in depth on two CAD frameworks called SCRIPT and RTL-PSC which evaluates information leakage through side-channel analysis at pre-silicon stage.

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Vorheriges Kapitel Security Assessment of High-Level Synthesis
Nächstes Kapitel Post-Quantum Hardware Security
Fußnoten
1
Stuck-at-fault is modeled by assigning a fixed logic value (0 or 1) to a single net or port of a design [34].
 
2
This seed is the same as TVLA’s setup [43] and 1000 plaintexts are enough to estimate SCA leakage based on our experiments.
 
3
The SRem represents the empirical SR based on actual SCA attacks with n plaintexts.
 
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Metadaten
Titel
CAD for Side-Channel Leakage Assessment
verfasst von
Adib Nahiyan
Miao (Tony) He
Jungmin Park
Mark Tehranipoor
Copyright-Jahr
2021
Buch
Emerging Topics in Hardware Security

Print ISBN: 978-3-030-64447-5

Electronic ISBN: 978-3-030-64448-2

Copyright-Jahr: 2021

DOI
https://doi.org/10.1007/978-3-030-64448-2_7

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