Challenges and Solutions for Very Low Energy Computation

This chapter addresses the main challenges, limits and possible solutions for strongly reducing the energy per binary switching. Several paths are possible: the adiabatic logic using a slow clock, which cannot be used for high performance devices, logic stochastic resonance, feedback-controlled dynamic gate, or conventional logic with a reduction in the stored energy, therefore a decrease of device capacitance C (device integration) or applied bias V _dd , which seems to be the most promising for future ICs. The reduction of the stored energy in conventional logic can be done with a strong reduction of V _dd using new physics and/or devices with 60 or sub-60 mV/dec subthreshold swing S, in particular with the main following concepts: energy filtering (Tunnel FET, with MOS—nanowires (NW)—carbon nanotube (CNT)—or Graphene, using band-to-band tunnelling to filter energy distribution of electrons in the source), internal voltage step-up (Ferroelectric gate FET, inducing a negative capacitance to amplify the change in channel potential induced by the gate), Nano-Electro-Mechanical-Structures, or Impact Ionisation MOS devices. We will focus here on the best ones, Tunnel FETs realized with ultrathin films, multi-gates and/or alternative channel materials, which could lead to ultra short channel devices with a strong reduction of the applied bias, together with very good performance and reliability.