nach oben

Erschienen in:

2012 | OriginalPaper | Buchkapitel

1. Challenges of Power Electronic Packaging

verfasst von : Yong Liu

Erschienen in: Power Electronic Packaging

Verlag: Springer New York

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config

KI-gestützte Suche

Aus

Abstract

Over the last 2 decades, power semiconductor technology has made impressive progress, particularly in increasing the high power density of monolithic, system module, and hybrid designs (State of the art and trends in power integration, pp 20–29, 1999; Evolution of the classical functional integration toward a 3D heterogeneous functional integration, pp 23–34, 2007), which are the driving forces toward a power system module, power system in package (SiP), and 3D power package with heterogeneous functional integration.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

über 102.000 Bücher
über 537 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Finance + Banking
Management + Führung
Marketing + Vertrieb
Maschinenbau + Werkstoffe
Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

über 67.000 Bücher
über 390 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Maschinenbau + Werkstoffe

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Nächstes Kapitel Power Package Electrical Isolation Design

Sanchez JL (1999) State of the art and trends in power integration. In: Proceedings of modeling and simulation of microsystem conference (MCM), Puerto Rico, USA, pp 20–29

Sanchez JL et al (2007) Evolution of the classical functional integration towards a 3D heterogeneous functional integration. In: Proceedings of 14th international conference on MIXEDS, Ciechocinek, Poland, pp 23–34

Lorenz L (2007) Key power semiconductor devices and development trends, physics of semiconductor device. In: IWPSD 2007, Mumbai, India, pp 743–750

Shen ZJ, Omura I (2007) Power semiconductor device for hybrid, electric, and fuel cell vehicles. Proc IEEE 95(4):778–789CrossRef

Emadi A, Lee YJ, Rajashekara K (2008) Power electronics and motor drives in electric, hybrid electric, and plug-in hybrid electric vehicles. IEEE Trans Ind Electron 55(6):2237–2245CrossRef

Caramel C et al (2008) The Bi-IGBT: a low losses power structure by IGBT parallel association. Semicond Sci Technol 23:1–8CrossRef

Ramdani J. Next generation power device. IEEE maine EDS Lecture, May 2010

Wolfgang E, Harder T (2008) Power electronic technology roadmap—a bottom up approach. In: Proceedings of 5th international conference on integrated power electronics systems, Nuremberg, Germany, pp 315–317

Bolannos MA (2005) Semiconductor IC packaging technology challenges: the next five years. In: EMAP2005, Tokyo, Japan

10.

Desbiens D (2005) Trends in power semiconductor packaging. In: Eurosime 2005, Berlin (keynote)

11.

Zhang K (2006) ENIAC and its strategic research agenda of more than Moore. In: Eurosime 2006, Italy (keynote)

12.

Cognetti C (2006) Semiconductor packaging: present and future. In: Eurosime 2006, Italy (keynote)

13.

Wolf MJ, Reichl H (2007) From microelectronic packaging to system integration. In: Eurosime2007, London (keynote)

14.

Poupon G (2007) SIP and 3D development, Eurosime2007, London (keynote)

15.

Lee R (2006) Development of WL packaging processes for 3D multi-flip chip stacking. In: IEEE ED society Maine chapter, 2006 (Invited talk)

16.

Shimaamoto H (2007) Technical trend of 3D chip stacked MCP/SIP. In: ECTC57 workshop, 2007

17.

Orii Y, Nishio T (2007) Ultra thin PoP technologies using 50 um pitch flip chip C4 interconnection. In: ECTC57 workshop, 2007

18.

Meyer-Berg G. Future packaging trends. In: Eurosime2008, Germany (keynote)

19.

Vardaman EJ (2008) Trends in 3D packaging. In: ECTC58 short course, 2008

20.

Fontanclli A (2008) System-in-package technology: opportunities and challenges. In: Proceedings of 9th international symposium on quality electronic design, 2008, pp 589–593

21.

Charboneau BC (2005) Double—sided liquid cooling for power semiconductor devices using embedded power packaging. In: IAS 2005, Hong Kong, pp 1138–1141

22.

Hashimoto T et al (2008) System in package with mounted capacitor for reduced parasitic inductance in voltage regulators. In: Proceedings of the 20th international sympoosium on power semiconductor devices & ICs, Orlando, FL, May 2008, pp 315–318

23.

The international technology roadmap for semiconductors (ITRS), SIP white paper v9.0, Assembly and packaging: system level integration in the package (SIP), SEMATECH, Austin, 2010

24.

Vanam K et al (2005) A novel packaging methodology for spray cooling of power semiconductor device using dielectric liquids. In: Annual Applied power electronics conference exposition APEC, March 2005, pp 2014–2018

25.

Prasher RS et al (2005) Nano and micro technology-based next-generation package-level cooling solutions. Intel Technol 9(4):285–296, http://www.intel.com, 2005

26.

Liu Y, Kinzer D (2011) Challenges of power electronic packaging and modeling. In: EuroSimE 2011, Linz, Austria (Keynote)

Titel: Challenges of Power Electronic Packaging
verfasst von: Yong Liu
Verlag: Springer New York
Buch: Power Electronic Packaging
Print ISBN: 978-1-4614-1052-2

Electronic ISBN: 978-1-4614-1053-9

Copyright-Jahr: 2012
DOI: https://doi.org/10.1007/978-1-4614-1053-9_1