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Erschienen in:
2014 | OriginalPaper | Buchkapitel
Chapter 18 Week 9 Class 1
verfasst von : John Michael Williams
Erschienen in: Digital VLSI Design with Verilog
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Abstract
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Lecture on timing checks and pulse controlsTopics: Relation to assertions, the twelve verilog timing checks, pulse filtering and delay pessimism.Summary: This will complete our study of timing issues in verilog, as well as of the allowed contents of a
specifyblock. We start by discussing the relationships among timing checks, assertions, and system tasks. After introducing the time-stamp/time-check rationale, we present the 12 timing checks and their default arguments. After describing conditioned events and timing-check notifiers, we explain verilog simulator pulse handling, inertial delay, thePATHPULSEtask, and pessimism reduction in thespecifyblock. -
Lab on timing checksWe exercise the timing checks and pulse-filtering features of
specifyblocks. -
Lab PostmortemWe entertain a Q&A session only, this time.