New Acceleration Techniques for Simulation-Based Fault-Injection

Abstract

Several important application sectors increasingly require the design of fault-tolerant circuits; reducing the cost and design time asks for a new generation of CAD tools, able to efficiently validate the adopted fault-tolerant mechanisms. This paper outlines a fault-injection platform supporting the injection of transient faults in VHDL descriptions. New techniques are proposed to speed-up fault-injection campaigns without any loss in terms of gathered information. Experimental results are provided, showing that the proposed techniques are able to reduce the total time required by fault-injection campaigns by at least one order of magnitude.