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Über dieses Buch

This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units. The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

Abstract
The scaling of CMOS technology to the nanometer regime inevitability increases reliability concerns, profoundly impacting all aspects of circuit performance and posing a fundamental challenge to future IC design. These reliability concerns arise from many different sources, and become more severe with continuous scaling.
Ricardo Reis, Yu Cao, Gilson Wirth

Chapter 2. Recent Trends in Bias Temperature Instability

Abstract
The paradigm shifts occurring in the past few years in our understanding of BTI are reviewed. Among the most significant ones is the shift from perceiving NBTI in terms of the ReactionDiffusion model to analyzing BTI with the tools originally developed for describing lowfrequency noise. This includes the interpretation of the time, temperature, voltage, and duty cycle dependences of BTI. It is further demonstrated that a wealth of information about defect properties can be obtained from deeplyscaled devices, and that this information can allow projection of variability issues of future deeply downscaled CMOS devices. The chapter is concluded by showing the most promising technological solutions to alleviate both PBTI and NBTI.
B. Kaczer, T. Grasser, J. Franco, M. Toledano-Luque, J. Roussel, M. Cho, E. Simoen, G. Groeseneken

Chapter 3. Charge Trapping Phenomena in MOSFETS: From Noise to Bias Temperature Instability

Abstract
Charge trapping phenomena is known to be a major reliability concern in modern MOSFETS, dominating low-frequency noise behavior and playing a significant role in aging effects such as Bias Temperature Instability (BTI). In this chapter we address this reliability issue.
Gilson Wirth, Roberto da Silva

Chapter 4. Atomistic Simulations on Reliability

Abstract
Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been researched as a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation—two key metrics for benchmark performance of digital and analog integrated circuits. In the following chapter, the authors have highlighted the random dopant fluctuation (RDF) based Ensemble Monte Carlo (EMC) device simulation study conducted by the Computational Electronics (COMPUTEL) research group of Arizona State University. In addition to RDF, random number and position of interface traps lying close to Si:SiO2 interface engender additional concerns leading to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this chapter present novel EMC based simulation studies on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length MOSFET device. From the observed simulation results and their analysis, it can be cogently projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the typical RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed and explained from analytical device physics perspectives.
Dragica Vasileska, Nabil Ashraf

Chapter 5. On-Chip Characterization of Statistical Device Degradation

Abstract
Bias temperature instability (BTI) is one of the most critical degradation mechanisms that occur in modern semiconductor devices. The degradation due to BTI is transient, and known to be greatly influenced by bias voltages and temperature, making it very difficult to detect possible BTI-related failures during manufacturing test. Characterization and modeling of BTI is hence extremely important to protect a chip from BTI-related failures. In this chapter, an array structure that accelerates the statistical characterization of BTI is described. By overlapping the stress-application period for each device, measurements on hundreds or thousands of devices can be conducted concurrently. Test chip measurement results that provides a statistical insight on the parameters of BTI-related degradation process are also presented.
Takashi Sato, Hiromitsu Awano

Chapter 6. Compact Modeling of BTI for Circuit Reliability Analysis

Abstract
The aging process due to Bias Temperature Instability (BTI) is a key limiting factor of circuit lifetime in contemporary CMOS design. Threshold voltage shift induced by BTI is a strong function of stress voltage and temperature. Furthermore, BTI consists of both stress and recovery phases, depending on the dynamic stress conditions. This behavior poses a unique challenge for long-term aging prediction for a wide range of stress patterns encountered in today’s circuits. Traditional approaches usually resort to an average, constant stress waveform to simplify the lifetime prediction. They are efficient, but fail to capture the reality of circuit operation, especially under Dynamic Voltage Scaling (DVS) or in analog/mixed signal designs where the stress waveform is much more random. In this chapter, we present a suite of modeling solutions that enable aging simulation under all dynamic stress conditions. The key innovation of this chapter is to develop compact models of BTI when the stress voltage is varying. The results cover the underlying physics of two leading mechanisms, Reaction–Diffusion (R–D) and Trapping/Detrapping (T–D). Moreover, silicon validation of these models is performed at 45 and 65 nm technology nodes, at both device and circuit levels. Leveraging the newly developed BTI models under DVS and random input waveforms, efficient aging simulation is demonstrated in representative digital and analog circuits. Our proposed work provides a general and comprehensive solution to circuit aging analysis under random stress patterns.
Ketul B. Sutaria, Jyothi B. Velamala, Athul Ramkumar, Yu Cao

Chapter 7. Circuit Resilience Roadmap

Abstract
Technology scaling has an increasing impact on the resilience of integrated circuits. This growth is the result of (a) increasing sensitivity to various noise sources, and (b) an increase in parametric variability. This chapter examines the issue of circuit resilience by studying ongoing trends in technology scaling. Additional experiments with basic circuit blocks, such as memory or logic cells, reveal insights into their behavior for future technology generations and major threats for circuit resilience.
Veit B. Kleeberger, Christian Weis, Ulf Schlichtmann, Norbert Wehn

Chapter 8. Layout Aware Electromigration Analysis of Power/Ground Networks

Abstract
In this chapter, we briefly introduce physical foundations of electromigration (EM) and present two classical EM-related theories. We discuss physical parameters affecting EM wire lifetime and we introduce some background related to the existing EM physical simulators. In our work, for EM physical simulation we adopt the atomic concentration balance-based model. We discuss the simulation setup and results. We present VEMA—a variation-aware electromigration (EM) analysis tool for power grid wires. The tool considers process variations caused by the chemical–mechanical polishing (CMP) and edge placement error (EPE). It uses a compact model that features critical region extraction and variation coefficient calculation. VEMA is a full-chip EM analysis tool; it extracts the effective jL product values and performs a via-centric EM lifetime calculation on ideally manufactured EM-mortal wires. It analyzes process variation effects on EM reliability and reports variation tolerances of EM-sensitive power grid wires.
Di-an Li, Malgorzata Marek-Sadowska, Sani R. Nassif

Chapter 9. Power-Gating for Leakage Control and Beyond

Abstract
The need of reliable nanometric integrated circuits is driving the EDA community to develop new automated design techniques in which power consumption and variability are central objectives of the optimization flow.
Although several Design-for-Low-Power and Design-for-Variability options are already available in modern EDA suites, the contrasting nature of the two metrics makes their integration extremely challenging. Most of the approaches used to compensate and/or mitigate circuit variability (e.g., Dynamic Voltage Scaling and Adaptive Body Biasing) are, in fact, intrinsically power inefficient, as they exploit the concept of redundancy, which is known to originate power overhead.
In this work, we introduce possible solutions for concurrent leakage minimization and variability compensation. More specifically, we propose Power-Gating as a mean for simultaneously controlling static power consumption and mitigating the effects induced by two of the most insidious sources of variability, namely, Process Variations (PV) due to uncertainties in the manufacturing and Transistor Aging due to Negative Bias Temperature Instability (NBTI).
We show that power-gating, when implemented through the insertion of dedicated switches (called sleep transistors), has a double effect: On one hand, when sleep transistors are enhanced with tunable features, it acts as a natural supply-voltage regulator, which implements a control knob for PV compensation; on the other hand, during the idle periods, it makes the circuits immune to NBTI-induced aging.
We describe optimization techniques for the integration of a new concept of power-gating into modern sub-45 nm design flows, that is, Variation-Aware Power-Gating. The experimental results we have obtained are extremely promising, since they show 100 % timing yield under the presence of PV and circuit lifetime extension of more than 5× in the presence of NBTI.
Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino

Chapter 10. Soft Error Rate and Fault Tolerance Techniques for FPGAs

Abstract
Different fault tolerance techniques can be applied to FPGAs according to their type of configuration technology, architecture and target operating environment. This chapter will present a set of fault mitigation techniques for SRAM, FLASH and ANTIFUSE-based FPGAs and a test methodology to characterize those FPGA under radiation. Results from neutron-induced faults will be presented and compared.
Fernanda Kastensmidt, Ricardo Reis

Chapter 11. Low Power Robust FinFET-Based SRAM Design in Scaled Technologies

Abstract
FinFETs have emerged as alternatives to conventional bulk MOSFETs in scaled technologies due to superior gate control of the channel, lower short channel effects and higher scalability. However, width quantization in FinFETs constrains the design space of FinFET-based circuits, especially SRAMs in which transistor sizing is critical for the circuit robustness. The adverse effects of width quantization can be mitigated by appropriate device-circuit co-design of FinFET-based memories. This chapter describes some of such techniques with an emphasis on the device-circuit interactions associated with each methodology. The impact of different technology options in FinFETs like gate-underlap, fin orientation, fin height, gate workfunction and independent control of the gates on the stability, power and performance of 6 T SRAMs is discussed.
Sumeet Kumar Gupta, Kaushik Roy

Chapter 12. Variability-Aware Clock Design

Abstract
High-performance clock network design has been a challenge for many years due to the drastically increasing effect of process variability. In addition, tight power budgets have lowered supply voltage levels which make designs more sensitive to noise. Together, variability and noise present a colossal challenge to clock designers in order to meet timing, yield, and power simultaneously. This chapter discusses the different strategies that designers use to ameliorate variability and noise problems in clock network design.
Matthew R. Guthaus, Gustavo Wilke
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