Skip to main content
Fachgebiete
Automobil + Motoren Bauwesen + Immobilien Business IT + Informatik Elektrotechnik + Elektronik Energie + Nachhaltigkeit Finance + Banking Management + Führung Marketing + Vertrieb Maschinenbau + Werkstoffe Versicherung + Risiko
DE
EN
Bücher
Zeitschriften
Themenseiten
Organisationspsychologie Projektmanagement Marketing Smart Manufacturing
Weitere Formate
Podcasts Webinare Technik Webinare Wirtschaft Kongresse Veranstaltungskalender Awards
Jetzt Einzelzugang starten
Zugang für Unternehmen
Referenzkunden
SLX-Digitalkonferenz: Zukunftswerkstatt 2024

Mehr Umsatz mit Top-Kontakten

Am 7. Mai erfahren Sie, wie Vertriebsteams Leadgenerierung, Leadnurturing und Leadstrategien effizient steuern können.
Erweiterte Suche
Anmelden
nach oben
Erschienen in:
Soft Errors from Space to Ground: Historical Overview, Empirical Evidence, and Future Trends Kapitel lesen Erstes Kapitel lesen

2011 | OriginalPaper | Buchkapitel

8. Circuit-Level Soft-Error Mitigation

verfasst von : Michael Nicolaidis

Erschienen in: Soft Errors in Modern Electronic Systems

Verlag: Springer US

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

In nanometric technologies, circuits are increasingly sensitive to various kinds of perturbations. Soft errors, a concern in the past for space applications, became a reliability issue at ground level. Alpha particles and atmospheric neutrons induce single-event upsets (SEUs) affecting memory cells, latches, and flip-flops, and single-event transients (SETs) initiated in the combinational logic and captured by the associated latches and flip-flops. To face this challenge, a designer must dispose a variety of soft-error mitigation schemes adapted to various circuit structures, design architectures, and design constraints. In this chapter, we describe several SEU and SET mitigation schemes that could help designers to meet their reliability constraints.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Jetzt informieren
Vorheriges Kapitel Integrated Circuit Qualification for Space and Ground-Level Applications: Accelerated Tests and Error-Rate Predictions
Nächstes Kapitel Software-Level Soft-Error Mitigation Techniques
Fußnoten
1
The implementation of the circuit and the evaluation of the technique are done by Thierry Bonnoit, Ph.D. student at TIMA lab.
 
Literatur
1.
Baumann R.C., Soft errors in advanced computer systems. IEEE Des. Test Comput. 22(3), 2005, 258–266
2.
Baumann R.C., Hossain T.Z., Murata S., Kitagwava H., Boron compounds as a dominant source of alpha particles in semiconductor devices. Proceedings of the 33rd International Reliability Physics Symposium, 1995
3.
Baze M., Buchner S., Attenuation of single event induced pulses in CMOS combinational logic. IEEE Trans. Nucl. Sci. 44(6), 1997, 2217–2223CrossRef
4.
Buchner S., Baze M., Brown D., McMorrow D., Melinger J., Comparison of error rates in combinational and sequential logic. IEEE Trans. Nucl. Sci. 44(6), 1997, 2209–2216CrossRef
5.
Benedetto J., Eaton P., Avery K., Mavis D., Turflinger T., Dodd P., Vizkelethyd G., Heavy ion-induced digital single-event transients in deep submicron processes. IEEE Trans. Nucl. Sci. 51, 2004, 3480–3485CrossRef
6.
Nicolaidis M., Scaling deeper to submicron: on-line testing to the rescue. Proceedings of the 28th Symposium on Fault-Tolerant Computing (FTCS-28), Munich, June 1998, pp. 299–301
7.
Nicolaidis M., Design for soft-error robustness to rescue deep submicron scaling. Proceedings of the IEEE International Test Conference, Washington, DC, October 18–23, 1998
8.
Nicolaidis M., Scaling deeper to submicron: on-line testing to the rescue. Proceedings of the 1998 IEEE International Test Conference (ITC 98), Washington, DC, October 1998
9.
Levendel I., Nicolaidis M., Abraham J.A., Abramovici M., Motto S., A D&T roundtable: on-line test. IEEE Des. Test Comput. 16(1), 1999, 80–86CrossRef
10.
Hawkins C.F., Baker K., Butler K., Figueras J., Nicolaidis M., Rao V., Roy R., Welsher T., IC reliability and test: what will deep submicron bring? IEEE Des. Test Comput. 16(2), 1999, 84–91CrossRef
11.
Roche P., Jacquet F., Caillat C., Schoellkopf J.P., An alpha immune and ultra low neutron SER high density SRAM. Proceedings of IRPS 2004, April 2004, pp. 671–672
12.
Nicolaidis M., Achouri N., Boutobza S., Dynamic data-bit memory built-in self-repair. Proceedings of the International Conference on Computer-Aided Design (ICCAD’03), San Jose, CA, November 9–13, 2003
13.
Hsiao M.Y., A class of optimal minimum odd-weight-column SEC-DED codes. IBM J. Res. Dev. 14(4), 1970, 395–401CrossRef
14.
Richter M., Oberlaender K., Goessel M., New linear SEC-DED codes with reduced triple bit error miscorrection probability. 14th IEEE International On-Line Testing Symposium, IOLTS’08, July 7–9, 2008, pp. 37–42
15.
Nicolaidis M., Electronic circuit assembly comprising at least one memory with error correcting means. French and US Patent pending, filed July 2001
16.
Nicolaidis M., Data storage method with error correction. French and US Patent pending, filed July 2002
17.
Nicolaidis M., Design for Soft-Error Mitigation. IEEE Trans. Device Mater. Reliab. 5(3), 2005, 405–418CrossRef
18.
Vargas F., Nicolaidis M., SEU tolerant SRAM design based on current monitoring. Proceedings of the 24th IEEE International Symposium on Fault-Tolerant Computing, Austin, TX, June 1994, pp. 106–115
19.
Gill B., Nicolaidis M., Wolff F., Papachristou C., Garverick S., An efficient BICS design for SEUs detection and correction in semiconductor memories. Proceedings of the Conference on Design, Automation and Test in Europe (DATE), 2005, pp. 592–597
20.
21.
Blahut R.E., Theory and practice of error control codes. Addison-Wesley, Reading, MA, 1983MATH
22.
Pradhan D.K., Fault-tolerant computing system design. Prentice-Hall, Englewood Cliffs, NJ, 1996
23.
Peterson W.W., Weldon E.J., Error-correcting codes, 2nd edn. MIT, Cambridge, MA, 1972MATH
24.
Koopman P., Chakravarty T., Cyclic redundancy code (CRC) polynomial selection for embedded networks. International Conference on Dependable Systems and Networks (DSN-2004), Florence, Italy, June 28–July 1, 2004, pp. 145–154
25.
Sklar B., Digital communications: fundamentals and applications. Prentice-Hall, Englewood Cliffs, NJ, 2001
26.
Nicolaidis M., A low-cost single-event latchup mitigation scheme. Proceedings of the 12th IEEE International Symposium on On-Line Testing, Como, Italy, July 10–12, 2006
27.
Nicolaidis M., Torki K., Natali F., Belhaddad F., Alexandrescu D., Implementation and validation of a low-cost single-event latchup mitigation scheme. IEEE Workshop on Silicon Errors in Logic – System Effects (SELSE), Stanford, CA, March 24–25, 2009
28.
Nicolaidis M., Circuit intégré protégé contre les courts-circuits et les erreurs de fonctionnement suite au passage d’une radiation ionisante. French Patent 2,882,601, delivered September 21, 2007
29.
Liu M.S., Shaw G.A., Yue J., Fabrication of stabilized polysilicon resistors for SEU control. US Patent, issued May 18, 1993
30.
Rockett L., An SEU hardened CMOS data latch design. IEEE Trans. Nucl. Sci. NS-35(6), 1988, 1682–1687CrossRef
31.
Whitaker S., Canaris J., Liu K., SEU hardened memory cells for a CCSDS Reed Solomon encoder. IEEE Trans. Nucl. Sci. NS-38(6), 1991, 1471–1477CrossRef
32.
Calin T., Nicolaidis M., Velazco R., Upset hardened memory design for submicron CMOS technology. 33rd International Nuclear and Space Radiation Effects Conference, Indian Wells, CA, July 1996
33.
Bessot D., Velazco R., Design of SEU-hardened CMOS memory cells: the HIT cell. Proceedings of the 1994 RADECS Conference, 1994, pp. 563–570
34.
Omana M., Rossi D., Metra C., Novel transient fault hardened static latch. Proceedings of the 18th International Test Conference, 2003, pp. 886–892
35.
Nicolaidis M., Perez R., Alexandrescu D., Low-cost highly-robust hardened storage cells using blocking feedback transistors. Proceedings of the IEEE VLSI Test Symposium, 2008, pp. 371–376
36.
Lin S., Kim Y.B., Lombardi F., A 11-transistor nanoscale CMOS memory cell for hardening to soft errors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010
37.
Moharam K., Touba N., Cost-effective approach for reducing the soft error failure rate in logic circuits. Proceedings of the International Test Conference (ITC), September 2003, pp. 893–901
38.
Dhillon Y.S., Diril A.U., Chatterjee A., Soft-error tolerance analysis and optimization of nanometer circuits. Proceedings of the Conference on Design, Automation and Test in Europe (DATE), March 7–11, 2005, pp. 288–293
39.
Zhou Q., Mohanram K., Cost-effective radiation hardening technique for combinational logic. Proceedings of the 2004 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 7–11, 2004, pp. 100–106
40.
Dhillon Y.S., Diril A.U., Chatterjee A., Metra C., Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits. Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS), July 6–8, 2005, pp. 35–40
41.
Siewiorek D.P., Swarz R.S., Reliable computer systems: design and evaluation. Digital Press, Bedford, MA, 1992
42.
Cheynet P., Nicolescu B., Velazco R., Rebaudengo M., Sonza Reorda M., Violante M., Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors. IEEE Trans. Nucl. Sci. 47(6), 2000, 2231–2236CrossRef
43.
Oh N., Mitra S., McCluskey E.J., ED4I: error detection by diverse data and duplicated instructions. IEEE Trans. Comput. 51(2), 2002, 180–199CrossRef
44.
Goloubeva O., Rebaudengo M., Sonza Reorda M., Violante M., Soft-error detection using control flow assertions. Proceedings of the 18th International Symposium on Defect and Fault Tolerance in VLSI Systems, Cambridge, MA, November 3–5, 2003, pp. 581–588
45.
Rebaudengo M., Sonza Reorda M., Violante M., A new approach to software-implemented fault tolerance. J. Electron. Test.: Theory Appl. 20, 2004, 433–437CrossRef
46.
Rebaudengo M., Sonza Reorda M., Violante M., Nicolescu B., Velazco R., Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparative study. IEEE Trans. Nucl. Sci. 49(3), 2002, 1491–1495CrossRef
47.
Alkhalifa Z., Nair V.S.S., Krishnamurthy N., Abraham J.A., Design and evaluation of system-level checks for on-line control flow error detection. IEEE Trans. Parallel Distrib. Syst. 10(6), 1999, 627–641CrossRef
48.
Oh N., Shirvani P.P., McCluskey E.J., Control-flow checking by software signatures. IEEE Trans. Reliab. 51(2), 2002, 111–122CrossRef
49.
Mukherjee S., Reinhardt S., Transient fault detection via simultaneous multithreading. International Symposium on Computer Architecture, June 2000
50.
Vijaykumar P.N., Pomerantz I., et al., Transient fault recovery using simultaneous multithreading. International Symposium on Computer Architecture, May 2002
51.
Mukherjee S., Kontz S., Reinhardt S., Detailed design and evaluation of redundant multithreading alternatives. International Symposium on Computer Architecture, May 2002
52.
Carter W.C., Schneider P.R., Design of dynamically checked computers. Proceedings of the 4th Congress IFIP, Vol. 2, Edinburgh, Scotland, August 5–10, 1968, pp. 878–883
53.
Anderson D.A., Design of self-checking digital networks using coding techniques. Coordinated Sciences Laboratory, Report R/527. University of Illinois, Urbana, IL, September 1971
54.
55.
Berger J.M., A note on error detection codes for asymmetric binary channels. Inform. Contr. 4, 1961, 68–73CrossRefMATH
56.
Peterson W.W., On checking an adder. IBM J. Res. Dev. 2, 1958, 166–168CrossRef
57.
Avizienis A., Arithmetic algorithms for error-coded operands. IEEE Trans. Comput. C-22(6), 1973, 567–572CrossRef
58.
Rao T.R.N., Error coding for arithmetic processors. Academic, New York, 1974MATH
59.
Nicolaidis M., Courtois B., Self-checking logic arrays. In: Microprocessors and microsystems. Butterworth Scientific Ltd, Guildford, UK, 1989
60.
De K., Natarajan C., Nair D., Banerjee P., RSYN: a system for automated synthesis of reliable multilevel circuits. IEEE Trans. VLSI Syst. 2(2), 1994, 186–195CrossRef
61.
Touba N.A., McCluskey E.J., Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection. Proceedings of the International Conference on Computer-Aided Design, 1994
62.
Nicolaidis M., Duarte R.O., Manich S., Figueras J., Achieving fault secureness in parity prediction arithmetic operators. IEEE Des. Test Comput. 14(2), 1997, 60–71CrossRef
63.
Nicolaidis M., Duarte R.O., Design of fault-secure parity-prediction booth multipliers. IEEE Des. Test Comput. 16(3), 1999, 90–101
64.
Duarte R.O., Nicolaidis M., Bederr H., Zorian Y., Efficient fault-secure shifter design. J. Electron. Test.: Theory Appl. 12, 1998, 29–39CrossRef
65.
Nicolaidis M., Carry checking/parity prediction adders and ALUs. IEEE Trans. VLSI Syst. 11(1), 2003, 121–128CrossRef
66.
Ocheretnij V., Goessel M., Sogomonyan E.S., Marienfeld D., A modulo p checked self-checking carry-select adder. 9th International On-Line Testing Symposium, July 2003
67.
Ocheretnij V., Marienfeld D., Sogomonyan E.S., Gossel M., Self-checking code-disjoint carry-select adder with low area overhead by use of add1-circuits. 10th IEEE International On-Line Testing Symposium, Madeira, Portugal, July 2004
68.
Smith J.E, Metze G., The design of totally self-checking combinatorials circuits. Proceedings of the 7th Fault-Tolerant Computing Symposium, Los Angeles, CA, June 1997
69.
70.
Diaz M., Design of totally self-checking and fail-safe sequential machines. Proceedings of the 4th International Fault-Tolerant Computing Symposium, Urbana, IL, 1974
71.
Diaz M., Geffroy J.C., Courvoisier M., On-set realization of fail-safe sequential machines. IEEE Trans. Comput. C-23, 1974, 133–138MathSciNetCrossRef
72.
Nanya T., Kawamura T., A note on strongly fault secure sequential circuits. IEEE Trans. Comput. C-36, 1987, 1121–1123CrossRef
73.
Mak G.P., Abraham J.A., Davindson E.S., The design of PLAs with concurrent error detection. Proceedings of the FTCS-12, Santa Monica, CA, June 1982
74.
Fuchs W.K., Chien Ch-H., Abraham J., Concurrent error detection in highly structured logic arrays. IEEE J. Solid-State Circuits SC-22, 1987, 583–594CrossRef
75.
Lo J.C., Thanawastien S., Rao T.R.N., Nicolaidis M., An SFS Berger check prediction ALU and its application to self-checking processors designs. IEEE Trans. Comput. Aided Des. 2(4), 1992, 525–540CrossRef
76.
Jha N.K., Wang S.-J., Design and synthesis of self-checking VLSI circuits. IEEE Trans. Comput. Aided Des. 12, 1993, 878–887CrossRef
77.
Sparmann U., On the check base selection problem for fast adders. Proceedings of the 11th VLSI Test Symposium, Atlantic City, NJ, April 1993
78.
Sparmann U., Reddy S.M., On the effectiveness of residue code checking for parallel two’s complement multipliers. Proceedings of the 24th Fault-Tolerant Computing Symposium, Austin, TX, June 1994
79.
Alzaher Noufal I., A tool for automatic generation of self-checking multipliers based on residue arithmetic codes. Proceedings of the 1999 Design, Automation and Test in Europe Conference, Munich, March 1999
80.
Nicolaidis M., Shorts in self-checking circuits. J. Electron. Test.: Theory Appl. 1(4), 1991, 257–273CrossRef
81.
Anghel L., Nicolaidis M., Alzaher Noufal I., Self-checking circuits versus realistic faults in very deep submicron. Proceedings of the 18th IEEE VLSI Test Symposium, Montreal, Canada, April 2000
82.
Alexandrescu D., Anghel L., Nicolaidis M., New methods for evaluating the impact of single event transients in VDSM ICs. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 2002
83.
Nicolaidis M., Fail-safe interfaces for VLSI: theoretical foundations and implementation. IEEE Trans. Comput. 47(1), 1998, 62–77CrossRef
84.
Nicolaidis M., Time redundancy based soft-error tolerant circuits to rescue very deep submicron. Proceedings of the 17th IEEE VLSI Test Symposium, Dana Point, CA, April 1999
85.
Anghel L., Nicolaidis M., Cost reduction and evaluation of a temporary faults detecting technique. Proceedings of the Design, Automation and Test in Europe Conference (DATE), Paris, March 2000
86.
Anghel L., Nicolaidis M., Cost reduction and evaluation of a temporary faults detecting technique. Chapter in The Most Influential Papers of 10 Years DATE, Springer Editions, ISBN: 978-1-4020-6487-6, 2008
87.
Nicolaidis M., Circuit Logique protégé contre des perturbations transitoires. French Patent application, filed March 9, 1999
88.
Ernst D., et al., Razor: a low-power pipeline based on circuit-level timing speculation. Proceedings of the 36th International Symposium on Microarchitecture, December 2003
89.
Ernst D., et al., Razor: circuit-level correction of timing errors for low-power operation. IEEE Micro 24(6), 2003, 10–20MathSciNetCrossRef
90.
Das S., et al., A self-tuning DVS processor using delay-error detection and correction. IEEE Symposium on VLSI Circuits, June 2005
91.
Agarwal M., Paul B.C., Ming Zhang Mitra S., Circuit failure prediction and its application to transistor aging. Proceedings of the 5th IEEE VLSI Test Symposium, Berkeley, CA, May 6–10, 2007
92.
Mitra S., Agarwal M., Circuit failure prediction to overcome scaled CMOS reliability challenges. IEEE International Test Conference, Santa Clara, CA, October 23–25, 2007
93.
Mitra S., Zhang M., Mak T.M., Kim K.S., System and shadow circuits with output joining circuit. US Patent 7,278,074, October 2, 2007, Assignee Intel
94.
Ming Zhang Mak T., Tschanz J., Kee Sup Kim Seifert N., Lu D., Design for resilience to soft errors and variations. 13th IEEE International On-Line Testing Symposium (IOLTS 07), July 2007, pp. 23–28
95.
Nicolaidis M., GRAAL: a new fault-tolerant design paradigm for mitigating the flaws of deep-nanometric technologies. Proceedings of the IEEE International Test Conference (ITC), Santa Clara, CA, October 23–25, 2007
96.
Piguet C., et al., Low-power design of 8-b embedded CoolRisc microcontroller cores. IEEE J. Solid-State Circuits 32(7), 1997, 1067–1078CrossRef
97.
Mack M.J., Sauer W.M., Mealey B.G., IBM POWER6 reliability. IBM J. Res. Dev. 51(6), 2007, 763–764CrossRef
98.
Bowman K.A., et al., Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance. IEEE J. Solid-State Circuits 44(1), 2009, 49–63CrossRef
99.
Franco P., McCluskey E.J., On-line testing of digital circuits. Proceedings of the IEEE VLSI Test Symposium, April 1994, pp. 167–173
100.
Metra C., Favalli M., Ricco B., On-line detection of logic errors due to crosstalk, delay, and transient faults. Proceedings of the International Test Conference, Washington, DC, October 18–23, 1998, pp. 524–533
101.
Hamming R.W., Error detecting and error correcting codes. Bell Syst. Tech. J. 29, 1953, 147–160MathSciNet
102.
Bose R.C., Ray-Chaundhuri D.K., On a class of error correcting binary group codes. Inform. Contr. 3(1), 1960, 68–79CrossRefMATH
103.
Metadaten
Titel
Circuit-Level Soft-Error Mitigation
verfasst von
Michael Nicolaidis
Copyright-Jahr
2011
Verlag
Springer US
Buch
Soft Errors in Modern Electronic Systems

Print ISBN: 978-1-4419-6992-7

Electronic ISBN: 978-1-4419-6993-4

Copyright-Jahr: 2011

DOI
https://doi.org/10.1007/978-1-4419-6993-4_8

Neuer Inhalt

    Bildnachweise