Circuit-level technique to design robust SRAM cell against radiation strike

In this paper, a 12-transistor radiation tolerant SRAM cell has been proposed in 16-nm CMOS predictive technology model. The proposed 12T SRAM cell offers higher immunity to soft error than all other compared memory cells. The proposed SRAM cell proves its robustness against radiation strike by showing the largest amount (4.1 fC) of critical charge (Q_C) among all the comparison SRAM cells. The proposed 12T cell consumes 48.03%, and 48.68% lower hold power than QUCCE 12T and QUCCE 10T SRAM cell, respectively. It exhibits 79.92%, 33.77%, 84.84%, and 59.97% shorter read delay compared to 6T SRAM, QUCCE 10T, WE QUATRO, and QUCCE 12T, respectively at a nominal supply voltage of 0.7 V. In terms of write delay the proposed 12T exhibits 68.49% shorter write delay as compared with QUCCE 10T. The proposed circuit has higher RSNM as compared to other SRAM cells and consumes lesser silicon area than other comparison cells except 6T and QUCCE 10T SRAM cell. The read stability of proposed 12T is 3.10×, 1.76×, 2.09×, 1.62 × times higher than 6T SRAM, QUCCE 10T, WE QUATRO, and QUCCE 12T, respectively. The proposed 12T exhibits 65.85%, 41.46%, 26.82%, and 41.46% improvement in critical charge (Q_C) in comparison with 6T SRAM, QUCCE 10T, WE QUATRO and QUCCE 12T, respectively. However, these improvements are achieved at the cost of marginal degradation of write margin as compared to 6T, QUCCE 10T, WE QUATRO and QUCCE 12T SRAM cells, respectively. In terms of area, the proposed 12T acquires lesser area as compared to QUCCE 12T (6.32%) and WE QUATRO (12%). Hence, the proposed 12T SRAM cell is a promising selection for future highly reliable terrestrial applications.