Skip to main content
Erschienen in: Journal of Electronic Testing 4/2021

30.09.2021

Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits

verfasst von: Tsai-Chieh Chen, Chia-Cheng Pai, Yi-Zhan Hsieh, Hsiao-Yin Tseng, James Chien-Mo, Tsung-Te Liu, I-Wei Chiu

Erschienen in: Journal of Electronic Testing | Ausgabe 4/2021

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

It is a real challenge to test asynchronous circuits since there is no clock signal, and there are many non-scan state-holding elements. In this paper, we first propose an Asynchronous Circuit Scan (A-SCAN) latch, which can flip between Valid and Empty states so that we can shift in and out without any clock. Experimental results show that our DFT area and power overhead are 28% and 104% smaller than previous synchronous DFT, respectively. The timing overhead of DFT is nearly two times smaller than previous asynchronous DFT. Based on A-SCAN, we propose the Asynchronous Built-in Self Test (A-BIST), which has no clock. Experimental results show that our BIST area and power overhead are 30% and 116% smaller than previous synchronous counterpart, respectively. Our test coverage is similar to that of ATPG. With A-SCAN and A-BIST, we can easily integrate synchronous and asynchronous testing on the same chip.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Weitere Produktempfehlungen anzeigen
Literatur
1.
Zurück zum Zitat Akopyan F, Sawada J, Cassidy A et al (2015) TrueNorth: design and tool flow of a 65 mW 1 Million neuron programmable neurosynaptic chip. IEEE Trans Comput Des Integr Circuits System 34(10):15371557 Akopyan F, Sawada J, Cassidy A et al (2015) TrueNorth: design and tool flow of a 65 mW 1 Million neuron programmable neurosynaptic chip. IEEE Trans Comput Des Integr Circuits System 34(10):15371557
2.
Zurück zum Zitat Al-Assadi WK, Kakarla S (2009) “Design for test of asynchronous NULL convention logic (NCL) circuits.” J Electron Test 25(1):117–126 Al-Assadi WK, Kakarla S (2009) “Design for test of asynchronous NULL convention logic (NCL) circuits.” J Electron Test 25(1):117–126
3.
Zurück zum Zitat Beest F, Peeters A, Verra M, van Berkel K, Kerkhoff H (2002) Automatic scan insertion and test generation for asynchronous circuits. Proc IEEE Test Conference pp. 804–813 Beest F, Peeters A, Verra M, van Berkel K, Kerkhoff H (2002) Automatic scan insertion and test generation for asynchronous circuits. Proc IEEE Test Conference pp. 804–813
4.
Zurück zum Zitat Beign E, Vivet P, Thonnart Y, Christmann JF, Clermidy F (2016) Asynchronous circuit designs for the Internet of everything: A methodology for ultralow-power circuits with gals architecture. IEEE Solid-State Circuits Mag. 8(4):39–47CrossRef Beign E, Vivet P, Thonnart Y, Christmann JF, Clermidy F (2016) Asynchronous circuit designs for the Internet of everything: A methodology for ultralow-power circuits with gals architecture. IEEE Solid-State Circuits Mag. 8(4):39–47CrossRef
5.
Zurück zum Zitat Chang J, Park SP, Roy K (2010) Exploring asynchronous design techniques for process-tolerant and energy-efficient subthreshold operation. IEEE J Solid-State Circuits 45(2):401–410CrossRef Chang J, Park SP, Roy K (2010) Exploring asynchronous design techniques for process-tolerant and energy-efficient subthreshold operation. IEEE J Solid-State Circuits 45(2):401–410CrossRef
6.
Zurück zum Zitat Chang K-L et al (2013) “Synchronous-logic and asynchronous-logic 8051 microcontroller cores for realizing the internet of things: A comparative study on dynamic voltage scaling and variation effects” IEEE. J Emerg Sel Topics Circuits Syst 3(1):23–34CrossRef Chang K-L et al (2013) “Synchronous-logic and asynchronous-logic 8051 microcontroller cores for realizing the internet of things: A comparative study on dynamic voltage scaling and variation effects” IEEE. J Emerg Sel Topics Circuits Syst 3(1):23–34CrossRef
7.
Zurück zum Zitat Chelcea T, Nowick SM (2004) Robust interfaces for mixed-timing systems. IEEE Trans Very Large Scale Integr (VLSI) Syst 12(8):857873 Chelcea T, Nowick SM (2004) Robust interfaces for mixed-timing systems. IEEE Trans Very Large Scale Integr (VLSI) Syst 12(8):857873
8.
Zurück zum Zitat Cheng CH, Li JCM (2011) An asynchronous design for testability and implementation in thin-film transistor technology. J Electron Test pp. 193–201 Cheng CH, Li JCM (2011) An asynchronous design for testability and implementation in thin-film transistor technology. J Electron Test pp. 193–201
9.
Zurück zum Zitat Chow A, Coates W, Hopkins D (2007) A configurable asynchronous pseudorandom bit sequence generator. In IEEE International Symposium on Asynchronous Circuits and Systems p. 143152 Chow A, Coates W, Hopkins D (2007) A configurable asynchronous pseudorandom bit sequence generator. In IEEE International Symposium on Asynchronous Circuits and Systems p. 143152
10.
Zurück zum Zitat Fant KM, Brandt SA (1996) Null Conventional Logic: A complete and consistent logic for asynchronous digital circuit synthesis. In International Conference on ASAP p. 261273 Fant KM, Brandt SA (1996) Null Conventional Logic: A complete and consistent logic for asynchronous digital circuit synthesis. In International Conference on ASAP p. 261273
11.
Zurück zum Zitat Hsieh S-A et al (2018) “DR-scan: Dual-rail asynchronous scan DfT and ATPG.” IEEE Trans Comput Aided Des Integr Circuits Syst Hsieh S-A et al (2018) “DR-scan: Dual-rail asynchronous scan DfT and ATPG.” IEEE Trans Comput Aided Des Integr Circuits Syst
12.
Zurück zum Zitat Huang K-Y, Shen T-Y, Li JC-M (2017) “Test methodology for dual-rail asynchronous circuits.” Design Automation Conference (DAC), 2017 54th ACM/EDAC/IEEE Huang K-Y, Shen T-Y, Li JC-M (2017) “Test methodology for dual-rail asynchronous circuits.” Design Automation Conference (DAC), 2017 54th ACM/EDAC/IEEE
13.
Zurück zum Zitat Iwata H et al (2010) “Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits.” In Proc 19th IEEE Asian Test Symposium Iwata H et al (2010) “Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits.” In Proc 19th IEEE Asian Test Symposium
14.
Zurück zum Zitat Kang Y-S, Huh, K-H, Kang S (1999) “New scan design of asynchronous sequential circuits.” 1st IEEE Asia Pacific Conference on ASICs pp. 355–358 Kang Y-S, Huh, K-H, Kang S (1999) “New scan design of asynchronous sequential circuits.” 1st IEEE Asia Pacific Conference on ASICs pp. 355–358
15.
Zurück zum Zitat Koppad D, Efthymiou A (2009) “BIST for strongly-indicating asynchronous circuits.” Very Large Scale Integration (VLSI-SoC), 17th IFIP International Conference on. IEEE Koppad D, Efthymiou A (2009) “BIST for strongly-indicating asynchronous circuits.” Very Large Scale Integration (VLSI-SoC), 17th IFIP International Conference on. IEEE
17.
Zurück zum Zitat Nemati N, Reed MC, Fant K, Beckett P (2016) “Asynchronous interleaved scan architecture for on-line built-in self-test of null convention logic.” IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC pp. 746–749 Nemati N, Reed MC, Fant K, Beckett P (2016) “Asynchronous interleaved scan architecture for on-line built-in self-test of null convention logic.” IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC pp. 746–749
18.
Zurück zum Zitat Petlin OA, Furber SB (1995) “Scan testing of micropipelines.” Proc 13th IEEE VLSI Test Symposium Petlin OA, Furber SB (1995) “Scan testing of micropipelines.” Proc 13th IEEE VLSI Test Symposium
19.
Zurück zum Zitat Petlin OA, Furber SB (1997) “Built-in self-testing of micropipelines.” Advanced Research in Asynchronous Circuits and Systems. Proceedings., Third International Symposium on. IEEE Petlin OA, Furber SB (1997) “Built-in self-testing of micropipelines.” Advanced Research in Asynchronous Circuits and Systems. Proceedings., Third International Symposium on. IEEE
20.
Zurück zum Zitat Sheibanyrad A, Greiner A (2008) Two efficient synchronous-asynchronous converters well-suited for network on chip in GALS architectures. Integration, the VLSI Journal 41(1):17–26CrossRef Sheibanyrad A, Greiner A (2008) Two efficient synchronous-asynchronous converters well-suited for network on chip in GALS architectures. Integration, the VLSI Journal 41(1):17–26CrossRef
21.
Zurück zum Zitat Smith SC, DeMara RF, Ferguson D, Lamb D (2004) Optimization of NULL convention self-timed circuits, submitted to Integration. The VLSI Journal Smith SC, DeMara RF, Ferguson D, Lamb D (2004) Optimization of NULL convention self-timed circuits, submitted to Integration. The VLSI Journal
22.
Zurück zum Zitat Spars JJ, Furber S (2001) Principles of asynchronous circuit design a system perspective. Kluwer Academic Publisher, Ch. 2-Ch. 3 Spars JJ, Furber S (2001) Principles of asynchronous circuit design a system perspective. Kluwer Academic Publisher, Ch. 2-Ch. 3
23.
Zurück zum Zitat Sutherland I, Fairbanks S (2001) GasP: A Minimal FIFO Control. Proc 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems 11:184–193 Sutherland I, Fairbanks S (2001) GasP: A Minimal FIFO Control. Proc 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems 11:184–193
24.
Zurück zum Zitat Teifel J, Manohar R (2004) Highly Pipelined Asynchronous FPGAs Proc. Int’l Symp. Field Programmable Gate Arrays Teifel J, Manohar R (2004) Highly Pipelined Asynchronous FPGAs Proc. Int’l Symp. Field Programmable Gate Arrays
25.
Zurück zum Zitat Zeidler S, Krsti M (2015) “A survey about testing asynchronous circuits.” IEEE European Conference on Circuit Theory and Design (ECCTD) Zeidler S, Krsti M (2015) “A survey about testing asynchronous circuits.” IEEE European Conference on Circuit Theory and Design (ECCTD)
Metadaten
Titel
Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits
verfasst von
Tsai-Chieh Chen
Chia-Cheng Pai
Yi-Zhan Hsieh
Hsiao-Yin Tseng
James Chien-Mo
Tsung-Te Liu
I-Wei Chiu
Publikationsdatum
30.09.2021
Verlag
Springer US
Erschienen in
Journal of Electronic Testing / Ausgabe 4/2021
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-021-05963-z

Weitere Artikel der Ausgabe 4/2021

Journal of Electronic Testing 4/2021 Zur Ausgabe