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The extreme ?exibility of recon?gurable architectures and their performance pot- tial have made them a vehicle of choice in a wide range of computing domains, from rapid circuit prototyping to high-performance computing. The increasing availab- ity of transistors on a die has allowed the emergence of recon?gurable architectures with a large number of computing resources and interconnection topologies. To - ploit the potential of these recon?gurable architectures, programmers are forced to map their applications, typically written in high-level imperative programming l- guages, such as C or MATLAB, to hardware-oriented languages such as VHDL or Verilog. In this process, they must assume the role of hardware designers and software programmers and navigate a maze of program transformations, mapping, and synthesis steps to produce ef?cient recon?gurable computing implementations. The richness and sophistication of any of these application mapping steps make the mapping of computations to these architectures an increasingly daunting process. It is thus widely believed that automatic compilation from high-level programming languages is the key to the success of recon?gurable computing. This book describes a wide range of code transformations and mapping te- niques for programs described in high-level programming languages, most - tably imperative languages, to recon?gurable architectures.



Chapter 1. Introduction

The increasing number of transistors on a chip [221,278] has enabled the emergence of reconfigurable architectures and systems with a wide range of implementation flavors [145, 308]. While they were once confined to glue-logic applications, given their very limited device capacities, reconfigurable architectures now cover a wide range of application domains, including high-performance computing where they deliver complete multicore solutions on a single chip [228, 270, 303]. The diversity of reconfigurable architectures is astounding. At one end of the spectrum, reconfigurable architectures are composed of a very large number of finegrained configurable elements as is the case in Field-Programmable-Gate-Arrays (FPGAs) [5, 14, 54, 111]. In this case, one can build very specialized storage and custom computing elements in response to specific domain requirements such as input data rates or stringent real-time requirements. At the other end of the spectrum, many computing cores such as general-purpose processors (GPPs) can be interconnected with other processors or memory via a customized reconfiguration network [37, 211, 303]. In between these two extremes lies a range of architectural options where multiple, and possibly heterogeneous, custom processing elements and storage structures can be interconnected in an almost infinite set of possibilities [145].
João M. P. Cardoso, Pedro C. Diniz

Chapter 2. Overview of Reconfigurable Architectures

In this chapter, we describe the main features of reconfigurable architectures and systems, focusing on reconfigurable fabrics, the underlying vehicle for reconfigurable computing. We begin with a short historical perspective followed by a description and categorization of reconfigurable architectural features, such as their granularity, interconnection topologies, and system-level integration. We describe dynamic reconfigurable features some architectures exhibit as well as the execution models these architectures preferentially expose. Throughout this chapter we illustrate specific architectural features using representative examples of commercial and academic reconfigurable architectures, but without aiming to survey all the efforts on reconfigurable computing architectures.
João M. P. Cardoso, Pedro C. Diniz

Chapter 3. Compilation and Synthesis Flows

When mapping applications to reconfigurable computing platforms composed of general-purpose processors (GPP) and reconfigurable architectures, compilers must assume the dual role of compiling for a known instruction-set architecture (ISA) and synthesizing an application-specific architecture to be implemented with the hardware resources of the underlying reconfigurable architecture. The compiler is thus responsible for the definition of the specific organization of the computing engine implemented in the reconfigurable processing units (RPUs). As reconfigurable systems offer the possibility of multiple processing elements (PEs), compilers must deal with the many aspects of parallel computing and all its associated compilation techniques, namely, processor synchronization, data partitioning, and code generation. It is thus not surprising that compilation for reconfigurable systems is notoriously hard as compilers must weave, in a coherent and effective way, techniques from parallel computing with techniques from traditional hardware synthesis.
João M. P. Cardoso, Pedro C. Diniz

Chapter 4. Code Transformations

In this chapter we describe various code transformations for reconfigurable architectures. We focus on transformations for which the ability of the architectures to provide custom/specialized hardware implementations increases their effectiveness in reducing, for example, execution time or hardware resource use.
João M. P. Cardoso, Pedro C. Diniz

Chapter 5. Mapping and Execution Optimizations

This chapter describes important aspects related to the mapping of computations to reconfigurable architectures. The inherently spatial nature of these architectures, their heterogeneity and the invariable limitations of its physical resources, makes this mapping an extremely challenging task. Compilers and tools must judiciously balance the use of different kinds of resources in space and time, engaging in algorithmic and mapping techniques similar to the ones used in the context of lowlevel hardware synthesis, albeit with mapping choices that can be leveraged at much higher levels of abstraction.
João M. P. Cardoso, Pedro C. Diniz

Chapter 6. Compilers for Reconfigurable Architectures

This chapter describes the most prominent academic efforts on compilation and synthesis of application codes written in high-level programming languages to reconfigurable architectures. The maturity of some of the compilation and mapping techniques described in Chaps. 4 and 5, and the stability of the underlying reconfigurable technologies, have enabled the emergence of commercial compilation solutions, such as the MAP compiler from SRC Computers [292] and the High-Level Compiler from Nallatech [223], both of which support the mapping of programs written in a subset of the C programming language to FPGAs.
João M. P. Cardoso, Pedro C. Diniz

Chapter 7. Perspectives on Programming Reconfigurable Computing Platforms

Despite tremendous progress in the development and integration of compilation and synthesis techniques, the challenging nature of the compilation and synthesis for reconfigurable architectures has defied the establishment of a de facto standard methodology. In this chapter, we begin by providing an overall perspective of what we believe is missing to make reconfigurable computing an ever increasing reality. We then outline several outstanding issues suggesting a set of research directions in compilation techniques for these architectures. In this context, we have focused on compilation techniques and have deliberately omitted system-level aspects of reconfigurable architectures such as dynamic reconfiguration and operating systemlevel services. We then describe a vision, albeit speculative, of a compilation flow augmented by the synergetic integration of language description and transformation specification techniques as well as the notion of resource virtualization. Finally, we discuss how reconfigurable technologies can play an important role in future VLSI devices where unreliability is an important issue [57, 130]. In this context, we highlight how compilation techniques for reconfigurable architectures can also play a role in emerging nanotechnology systems.
João M. P. Cardoso, Pedro C. Diniz

Chapter 8. Final Remarks

Despite the tremendous progress made over the last decade, efficient automatic compilation from high-level programming languages to reconfigurable architectures, widely believed to be the key to make this promising technology the dominant computing paradigm, still remains an elusive goal.
João M. P. Cardoso, Pedro C. Diniz


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