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1990 | OriginalPaper | Buchkapitel

Compiling for the Hybrid Architecture

verfasst von : Robert A. Iannucci

Erschienen in: Parallel Machines: Parallel Machine Languages

Verlag: Springer US

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This chapter considers the task of transforming dataflow program graphs into partitioned graphs, and thence into PML. Section 4.1 extends the work of Section 1.1 by completing the description of DFPG’s. Section 4.2 discusses the issues involved in generating partitioned code from DFPG’s. Section 4.3 presents the design of a suitable code generator.

Metadaten
Titel
Compiling for the Hybrid Architecture
verfasst von
Robert A. Iannucci
Copyright-Jahr
1990
Verlag
Springer US
DOI
https://doi.org/10.1007/978-1-4613-1543-8_4

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