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examples are presented. These chapters are intended to introduce the reader to the programs. The program structure and models used will be described only briefly. Since these programs are in the public domain (with the exception of the parasitic simulation programs), the reader is referred to the manuals for more details. In this second edition, the process program SUPREM III has been added to Chapter 2. The device simulation program PISCES has replaced the program SIFCOD in Chapter 3. A three-dimensional parasitics simulator FCAP3 has been added to Chapter 4. It is clear that these programs or other programs with similar capabilities will be indispensible for VLSI/ULSI device developments. Part B of the book presents case studies, where the application of simu­ lation tools to solve VLSI device design problems is described in detail. The physics of the problems are illustrated with the aid of numerical simulations. Solutions to these problems are presented. Issues in state-of-the-art device development such as drain-induced barrier lowering, trench isolation, hot elec­ tron effects, device scaling and interconnect parasitics are discussed. In this second edition, two new chapters are added. Chapter 6 presents the methodol­ ogy and significance of benchmarking simulation programs, in this case the SUPREM III program. Chapter 13 describes a systematic approach to investi­ gate the sensitivity of device characteristics to process variations, as well as the trade-otIs between different device designs.

Inhaltsverzeichnis

Frontmatter

Overview

Overview

Abstract
In order to bring out the importance of Computer-Aided Design (CAD) in VLSI (Very-Large-Scale Integration) device design, it is nesessary to discuss the evolotion og the Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and the isses involved in its scaling. MOSFETs, first proposed 50 years ago, are based on the principle of modulating longitudinal electrical conductance by varying a transverse electrical field. Since its conception, MOSFET technology has improved steadily and has become the primarily because of the simple device structure. VLSI development for greater functional complexity and vircuit performance on a single chip is strongly motivated by the reduced cost per device and has been achieved in part by larger chop areas, but predominantly by smaller device dimensions and the clever design of devices and circuits.
Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

Numerical Simulation Systems

Frontmatter

Chapter 1. Numerical Simulation Systems

Abstract
Historically, numerical simulations of the MOS device have been used first to understand the device operation in the subthreshold and saturation regions. In 1969, Barron [1.1] from Stanford University simulated a MOSFET transistor using a finite-difference method to study the subthreshold conduction and saturation mechanism. Vandorpe [1.2] also simulated and modeled the saturation region with the finite-difference program in 1972. After the self-aligned silicon gate technology was invented, MOSFET device dimensions were reduced. This reduction prompted more numerical simulations to study the short-channel and narrow-width effects. Mock and Kennedy [1.3] from IBM developed a finite-difference program. Hatchel [1.4] also from IBM developed the first finite-element device simulation program. Barnes [1.5] from University of Michigan also developed a finite-element device simulation program for GaAs MESFETs. Most of the programs mentioned above were developed as research tools rather than as design tools for the general users. More emphasis had been put on the development of a stable and fast algorithm and the implementations of the physical mechanisms rather than on the user interface.
Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

Chapter 2. Process Simulation

Abstract
Silicon integrated circuit (IC) technology has evolved to fabricate multi-million transistors on a single chip. Trial-and-error methodology to optimize such a complex process is no longer desirable because of the enormous cost and turn-around time. From this point of view, computer simulation is a cost-effective alternative, not only supplying a right answer for increasingly tight processing windows, but also serving as a tool to develop future technologies. When coupled with a device analysis program, a process simulator has proven to be a powerful design tool because the process sensitivity to device parameters can be easily extracted by simple changes made to processing conditions in computer inputs [2.1].
Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

Chapter 3. Device Simulation

Abstract
As the dimensions of MOS devices are scaled down, the device structures become more complicated. The insulator/semiconductor interfaces are often non-planar, and the impurity profiles of the devices are complicated and may not be expressed accurately in Gaussian form. The increased complexity of the device structure is necessary for optimization of the device performance, such as minimizing the drain-induced barrier-lowering effects, or enhancing the device reliability, e.g., reducing the electric field at the drain of the MOSFET. Therefore, in the development of VLSI MOS technology, it is essential to be able to simulate the electrical characteristics of devices which have complicated structures. The GEMINI program provides this capability.
Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

Chapter 4. Parasitic Elements Simulation

Abstract
As we scale down the critical dimensions in integrated circuits, the effect of interconnects becomes as critical as that of devices on the overall circuit performance [4.1],[4.2]. The interconnect lines not only act as loads for their drivers but also become a source of noise because the lines are capacitively coupled when they are close to each other. Also, because we scale down the widths of the lines while the lengths of the lines are generally fixed, the resistance of the lines becomes larger. Generally, parasitic inductance is not of concern in on-chip interconnections. However, it is very critical in the packaging of integrated circuits. Careful characterization of these parasitic components in integrated circuits is essential to improve the performance of the circuits.
Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

Applications and Case Studies

Frontmatter

Chapter 5. Methodology in Computer-Aided Design for Process and Device Development

Abstract
The previous chapters have presented an overview of computer-aided design (CAD) in VLSI development, as well as the simulation tools currently used at Hewlett-Packard Laboratories. In this chapter, CAD is discussed from the user point of view. The methodology for using the simulation tools in the most effective way is presented. Then case studies will be presented in the following chapters which show in detail how simulation tools are used in device designs.
Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

Chapter 6. SUPREM III Application

Abstract
SUPREM III has emerged as the most widely used process simulator. The authors of SUPREM III have attempted to include the most up-to-date physically based process models that are currently available and suitable for computer simulation. Innumerable research hours have gone into the development of the various models and fitting parameters. However a silicon process, whether it is bipolar, NMOS, or CMOS, is an extremely complicated entity. There are several problems inherent in the SUPREM process models.
Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

Chapter 7. Simulation Techniques for Advanced Device Development

Abstract
In this chapter, the basic simulation techniques for advanced MOS device development will be described. First of all, the basic device physics of MOSFET is presented. The discussion will be in very simple terms, although sufficient to allow the process engineers to understand the basic characteristics of MOSFETS and their significance. The techniques of generating the device parameters are then presented. Also to be discussed are the short channel effects such as drain-induced barrier lowering. Simulations are used to reveal details of these phenomena. The relationship between process parameters and device characteristics are discussed. Simulated results are compared with experimental results. The SUPREM, GEMINI and PISCES programs are used for simulating the device characteristics.
Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

Chapter 8. Drain-Induced Barrier Lowering in Short Channel Transistors

Abstract
Drain-induced barrier lowering (DIBL) [8.1]-[8.6] has been studied by many workers. The result of DIBL is an increase in the residual leakage current in short channel devices as the drain to source voltage is increased. Fig. 8.1 shows the measurement of the drain to source current of a short channel MOSFET’s, as a function of the drain bias, for gate bias of 0 V. Note that the current increases exponentially with drain bias. Fig. 8.2 shows the simulated potential profile between the source and drain of a long and short channel MOSFET’s, with a drain to source bias of 9 V. The potential barrier between the source and the channel is lowered by the drain bias, for the short channel device. The drain to source leakage current is exponentially dependent on the potential barrier. This leakage current can cause many problems in circuits such as dynamic memories or low power circuits in battery operation environments. In the first example, if the pass transistor of the one-transistor dynamic memory cell [8.7] has significant leakage current, then the bit information of the cell may be lost. In the case of low power circuits, leakage current in the devices means much larger standby power. If severe leakage problems are present, the circuit may not function properly, especially for NMOS circuits.
Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

Chapter 9. A Study of LDD Device Structure Using 2-D Simulations

Abstract
In this chapter, analysis and design of LDD (Lightly Doped Drain) devices using two-dimensional device simulation and experiments will be described to illustrate the usefulness and necessity of using computer-aided design tools in the fabrication of VLSI devices. First, the problem of high electric field in VLSI devices and the use of LDD device as a possible solution is discussed. The fabrication and simulation of LDD device is then described. Finally, the performance, characteristic, physics and design considerations of LDD device are presented in detail.
Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

Chapter 10. The Surface Inversion Problem in Trench Isolated CMOS

Abstract
Trench isolation has recently been proposed for advanced CMOS processes [10.1]–[10.4]. Fig. 10.1 shows a trench isolated CMOS structure. The major advantage of trench isolation in CMOS is to reduce the latchup problem [10.5],[10.6]. Fig. 10.2 shows the latchup path for a CMOS structure, where the parasitic bipolar transistors are shown to form a positive feedback path. If there is excess current flow in the n-well and substrate, and if the substrate and n-well resistances are large enough, significant voltage drops will occur in the substrate and n-well. Under this condition, the parasitic bipolar transistors can be turned on [10.5]. This phenomenon has been studied by many researchers in CMOS technology. The trench has been suggested as a good candidate for isolation between n-channel and p-channel transistors. For an n-well process it is expected that the lateral n-p-n parasitic bipolar transistor gain will be reduced, thereby increasing the latchup initiating current. In a p-well process, the reduction of latchup sensitivity is achieved from reduction of the lateral parasitic p-n-p current gain.
Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

Chapter 11. Development of Isolation Structures for Applications in VLSI

Abstract
Device isolation has become one of the major issues in VLSI. As more and more devices are packed together on a single chip, the spacing between devices is reduced significantly. Island width/space design rules are becoming very aggressive, in the range of 1 μm/1 μm [11.1]. This means that the width of the isolation structures has to be scalable without causing field leakage problems. Also, as the transistor widths are scaled down, to the range of 2 μm or less, narrow width effects become a major issue [11.2]–[11.5]. These effects are dependent on the isolation structures since the channel width of the device is defined by the field isolation. Many novel isolation structures have been investigated for applications in VLSI [11.6]–[11.14].
Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

Chapter 12. Transistor Design for Submicron CMOS Technology

Abstract
In this chapter, the design of transistors for submicron CMOS technology will be presented. The advantages of, as well as issues involved in CMOS technology will first be discussed. Then the concerns for the design of n- and p-channel MOSFET’s with submicron channel lengths will be discussed. Using simulations, the values of the critical device parameters are determined which will minimize leakage problems in submicron transistors.
Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

Chapter 13. A Systematic Study of Transistor Design Traae-offs

Abstract
The ability to manufacture circuits at, or near, fundamental density and speed limits is affected by the sensitivity of circuit parameters to variations in the manufacturing process, and by the ability to achieve tight control of the manufacturing process. Modifications of device or circuit design can alter the various dependencies, so that parts of the process that are intrinsically more controllable determine critical circuit properties. Critical dimensions determined by a series of steps (mask-making, exposure, develop, etch) are typically held to + /- 20%. Various ion implant doses and depths can be controlled to + /- 2% to 5%. For example, if there is an absolute minimum for channel length, then the circuit design must be set at L min +ΔL, where the yield of devices with L >L min is satisfactory and ΔL is a measure of the process variation with gate line width. L min must also allow for some overlap of the gate to source and drain. If the minimum channel length is set by a reliability factor, then the design target is determined by allowable early field failures rather than the allowable yield. This illustrates the difficulty in understanding the problems associated with scaling critical dimensions to less than 0.5 μm.
Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

Chapter 14. MOSFET Scaling by CADDET

Abstract
The density and performance of integrated circuits have increased by many orders of magnitude through the process of device scaling. As pointed out in the overview chapter, the long channel relations are not strictly valid for horizontal dimensions that are comparable to the vertical dimensions. In this example, the operating voltage is kept constant. The horizontal dimension, L eff , and the vertical dimension, T ax , will be separately scaled to approximately two-thirds of the established process values. The two scaling factors are not identical, but are in the typical scaling range. The result of this reduction is then established. Comparison with the long-channel scaling assumptions is possible, and the importance of secondary physical effects can be seen. Device width will not be scaled, the current drive capability will be expressed for a fixed width. Breakdown and punchthrough voltages must be sufficiently greater than the supply voltage so that reliability is not a problem. For this example, power density is not a limitation.
Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

Chapter 15. Examples of Parasitic Elements Simulation

Abstract
In this chapter, the examples of parasitic component simulations are presented. The problems are solved by the appropriate simulation tools discussed in Chapter 4 and the other tools such as SUPREM, GEMINI, and SUPRA. Section 15.2 covers two-dimensional problems and section 15.3 deals with the problems which have to be solved by three-dimensional simulation. The experimental verification of the simulation results are also discussed.
Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

Backmatter

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