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Über dieses Buch

The subject of this book is the analysis and design of digital devices that implement computer arithmetic. The book's presentation of high-level detail, descriptions, formalisms and design principles means that it can support many research activities in this field, with an emphasis on bridging the gap between algorithm optimization and hardware implementation. The author provides a unified view linking the domains of digital design and arithmetic algorithms, based on original formalisms and hardware description languages.

A feature of the book is the large number of examples and the implementation details provided. While the author does not avoid high-level details, providing for example gate-level designs for all matrix/combinational arithmetic structures.

The book is suitable for researchers and students engaged with hardware design in computer science and engineering.

A feature of the book is the large number of examples and the implementation details provided. While the author does not avoid high-level details, providing for example gate-level designs for all matrix/combinational arithmetic structures.

The book is suitable for researchers and students engaged with hardware design in computer science and engineering.

Inhaltsverzeichnis

Frontmatter

Chapter 1. The Representation of Numbers in Computing Systems

The chapter contains fundamental notions referring to the number representations in computation, in fixed point and in floating point. As regards the fixed point, in distinct sections we analyze the binary numbers and decimal numbers representations. We present, together with their advantages and disadvantages, the representations of fixed point binary numbers in sign-magnitude, ones complement and twos complement codes, in particular aiming toward the addition operation. Referring to the floating point representations, the emphasis is on the issues concerning the biased representation of the exponent and the normalized representation of the mantissa. Moreover, the specific elements corresponding to the IEEE 754 floating point binary number representation standard are detailed.

Mircea Vlăduţiu

Chapter 2. Functional Analysis and Synthesis of Binary and Decimal Adding and Subtracting Devices

Following a brief presentation of the serial adder, the chapter approaches at large the problems of functional analysis and synthesis of the parallel addition and subtraction devices for binary and decimal numbers. The advantages and disadvantages of the parallel adders and subtracters based on the ripple carry principle are discussed both for binary numbers as well as for decimal numbers. Afterwards solutions for improving the performance with respect to the critical parameter represented by the maximal addition time are analyzed, based on the carry lookahead, carry-skip, carry-select and conditional-sum principles. Distinct sections are allocated to the parallel adders based on the carry save principle allowing for the synthesis of efficient multiplication devices, respectively to the parity checked adders allowing for the enhancement of reliability and dependability.

Mircea Vlăduţiu

Chapter 3. Functional Analysis and Synthesis of Binary Multiplication Devices

The chapter starts with the presentation of the fundamental methods for binary multiplication. Subsequently we introduce, in a unitary manner, syntheses of sequential multiplication devices for numbers represented in sign-magnitude code, respectively on twos complement code based on the Robertson and Booth procedures. The algorithms are presented in terms of a hardware description language accompanied by configuration diagrams, as well as by examples of operation, all emphasizing differences with respect to the performance-price-reliability triplet. Afterwards, techniques for multiplication process speedup are analyzed, based on raising the value of the number systems radix and use of a carry-save adder. There is a distinctive emphasis on combinational array and tree structures for binary multiplication implementation. Following the same direction of increased importance for the reliability and dependability aspects, similarly to the addition/subtraction chapter, we inserted a section addressing control by means of residue codes of the binary multiplication operation.

Mircea Vlăduţiu

Chapter 4. Functional Analysis and Synthesis of Binary Division Devices

Similarly to the chapter dedicated to the multiplication operation, this chapter begins with the presentation of the fundamental methods for binary division. In the same unitary manner used throughout the entire book, the synthesis of a sequential device for division is described, based on the non-restoring procedure for unsigned binary integer numbers. The description of the combinational array structures follows, which are favorable with respect to the hardware implementations of the binary division operation. Solutions are given for dividing signed fractional binary numbers based on the non-restoring procedure, respectively, for dividing unsigned binary integer numbers based on the restoring procedure. A distinct section is dedicated to the SRT procedures for binary division, both for radix-2 and for radix-4. The chapter concludes with a section dedicated to the division methods based on rapid convergence.

Mircea Vlăduţiu

Chapter 5. Functional Analysis and Synthesis of Floating Point Arithmetic Devices

The chapter is dedicated to the functional analysis and synthesis of the floating point arithmetic devices and it begins by highlighting the characteristics of operating in floating point, with investigation of the fundamental operations of addition, subtraction, multiplication and division. Particular consideration is given to the rounding problem with respect to analyzing the rounding modes, establishing the values of the rounding bits following the normalization shifts and of the conditioned implementation of the rounding operation. Synthesis solutions for some floating point units are presented, for which the addition and subtraction operations are to be realized without and with rounding. The steps of the algorithm for floating point addition and subtraction with rounding are dissected and the methods for speeding up the addition/subtraction process are investigated. Besides the speedup techniques based on an arithmetic pipeline, there is an extensive presentation of the solutions based on parallel computation. In this last context we present some innovative solutions based on reconfigurable synthesis. The chapter concludes with a section dedicated to analysis of the floating point multiplication and division operations.

Mircea Vlăduţiu

Backmatter

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