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2017 | Buch

The Evolution of Software-Defined Radio: An Introduction Kapitel lesen Erstes Kapitel lesen

Computing Platforms for Software-Defined Radio

herausgegeben von: Waqar Hussain, Jari Nurmi, Jouni Isoaho, Fabio Garzia

Verlag: Springer International Publishing

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik"

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Über dieses Buch

This book addresses Software-Defined Radio (SDR) baseband processing from the computer architecture point of view, providing a detailed exploration of different computing platforms by classifying different approaches, highlighting the common features related to SDR requirements and by showing pros and cons of the proposed solutions. It covers architectures exploiting parallelism by extending single-processor environment (such as VLIW, SIMD, TTA approaches), multi-core platforms distributing the computation to either a homogeneous array or a set of specialized heterogeneous processors, and architectures exploiting fine-grained, coarse-grained, or hybrid reconfigurability.

Inhaltsverzeichnis

Frontmatter
Chapter 1. The Evolution of Software-Defined Radio: An Introduction
Abstract
The Software-Defined Radio (SDR) concept was originally developed by the combined efforts of various research groups in the private and government organizations of the United States (US) in 1970s–1980s. The important ones to mention are the US Department of Defense Laboratory and a team at the Garland, Texas Division of E-Systems Inc. In 1991, Joe Mitola independently reinvented the term ‘Software Radio’ (SR) in cooperation with E-Systems as a plan to build a true software-based GSM transceiver (Mitola, Telesystems Conference, 1992). The SR platform essentially processes almost all the transceiver algorithms as software for a processor. This includes nearly all layers of transmission. However, an optimal implementation of physical layer is always challenging due to an enormous amount of mathematical computation. Over the period of time, many developmental changes occurred and an interesting feature of cognition was added to existing SDR platforms, thereby inventing the term ‘Cognitive Radio’. The main idea was to reduce over-sampling by the analog to digital converter, reduce on-chip processing and to target only the spectrum of interest. This book also touches the CR feature in the large SDR field in some of its selected chapters. Since, the very first few articles of J. Mitola, there has a been a tremendous amount of research work conducted in industry and academia. The evolution in SDRs is continuous with time and provides a number of excellent opportunities to researcher for exploration and to come up with their findings. The present day SDR implementations are such that the designers are focused mostly on the design of hardware and software, their interfacing and optimizations for varying architectural choices. It includes multiple cases of application-specific general-purpose acceleration platforms that are scalable, homogeneous and heterogeneous in nature while providing multiple programmable cores on a single chip computing system.
Waqar Hussain, Jouni Isoaho, Jari Nurmi

Architectures, Designs and Implementations

Frontmatter
Chapter 2. Design Transformation from a Single-Core to a Multi-Core Architecture Targeting Massively Parallel Signal Processing Algorithms
Abstract
This chapter describes single-core and multi-core platforms that are reconfigurable and heterogeneous by design and are specifically targeted to accelerate computationally intensive signal processing algorithms mostly used in software-designed radio applications. The signal-core accelerator architectures are tightly integrated with a C programmable processor core while the backbone of communications and control in multi-core architecture is a network-on-chip. The platforms were instantiated multiple times for different proof-of-concept application scenarios. The single- and multi-core platforms were subjected to self-aware dynamic frequency scaling while being prototyped for a field programmable gate array device. The performance of the platforms was measured and estimated in terms of many basic and high-level metrics and comparisons with other state-of-the-art platform are established for design evaluation.
Waqar Hussain, Henry Hoffmann, Tapani Ahonen, Jari Nurmi
Chapter 3. The CoreVA-MPSoC: A Multiprocessor Platform for Software-Defined Radio
Abstract
The advancement in performance of mobile devices goes hand in hand with increasing demand for communication bandwidth. In the past decade an almost unmanageable number of different wireless communication standards has emerged. In addition, the complexity of many of those standards has led to a steadily increasing demand for high performance modem signal processing. Future SDR baseband processing can significantly benefit from the massive parallelism provided by homogeneous many-core architectures. In this chapter, the CoreVA-MPSoC is presented as an example of an embedded hierarchical multiprocessor architecture for SDR processing. Parallelism is introduced at different levels of the CoreVA-MPSoC: basic building block is the resource-efficient VLIW processor CoreVA, providing fine-grained concurrency at the instruction level. Multiple CoreVA CPUs are combined within a CPU cluster and connected via a high speed, low latency interconnect. Finally, a dedicated Network on Chip is used to combine an arbitrary number of CPU clusters on a single chip. In addition to the hardware architecture, an MPSoC compiler for streaming applications is presented and utilized for the mapping of SDR applications to the CoreVA-MPSoC under throughput, latency, energy, and memory constraints.
Gregor Sievers, Boris Hübener, Johannes Ax, Martin Flasskamp, Wayne Kelly, Thorsten Jungeblut, Mario Porrmann
Chapter 4. Design and Implementation of IEEE 802.11a/g Receiver Blocks on a Coarse-Grained Reconfigurable Array
Abstract
This chapter presents the design and evaluation of template-based Coarse-Grained Reconfigurable Array (CGRA) generated accelerators that process Orthogonal Frequency-Division Multiplexing receiver blocks. The CGRA operates as a coprocessor with a Reduced Instruction-Set Computing (RISC) processor so that the overall system yields the benefits of general- and special-purpose processing. The accelerators are designed by crafting the CGRA template to the computational and communication requirements of the algorithms in an effort to minimize the resource utilization and power dissipation on the target Field Programmable Gate Array (FPGA) device. The performance of each CGRA is recorded in terms of the number of clock cycles and several multiple performance metrics. The power consumption is also estimated by simulating the postfit gate-level FPGA netlist of the accelerators.
Sajjad Nouri, Waqar Hussain, Diana Göhringer, Jari Nurmi
Chapter 5. Reconfigurable Multiprocessor Systems-on-Chip
Abstract
Software Defined Radios (SDRs) require architectures with a high flexibility to support multi-mode and multi-standard receivers and transmitters. In addition, these architectures need to fulfill the contradicting requirements of high performance for processing high data rates and low power consumption to be deployable in mobile devices. As the market for SDR is evolving, a scalable and adaptive architecture is desired to be able to upgrade the architecture to provide the needed computing performance for future use cases. This chapter highlights the requirements of high flexibility, high performance, low power, and high scalability and presents a solution to fulfill these requirements using runtime reconfigurable Multi-Processor Systems-on-Chip (MPSoCs).
Diana Goehringer
Chapter 6. Ninesilica: A Homogeneous MPSoC Approach for SDR Platforms
Abstract
This chapter presents the study of Software Defined Radio applications on homogeneous multi-core architectures based on the Silicon Café template. Two instances of the template have been realized and implemented on an Altera Stratix IV FPGA device. Ninesilica, the first instance of the template, is a homogeneous 3 × 3 mesh of processing elements realizing a standalone cluster. The second instance of the template is a clustered architecture composed of four Ninesilica clusters. Significant kernels of WCDMA and OFDM kernels were ported on the architectures analyzing the platform performance in terms of computational power, algorithm scalability, energy consumption and efficiency, portability of the mapping and hardware scalability. The achieved results showed that the proposed approach offers a high flexibility and parallelization efficiency, making homogeneous solutions a good candidate for the implementation of SDR systems.
Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Jari Nurmi

Software-Based Radio Cognition and Implementation Tools

Frontmatter
Chapter 7. Application of the Scalable Communications Core as an SDR Baseband
Abstract
Today’s consumers expect the connectivity of data anywhere and at anytime, i.e., voice and media for their smartphones, notebooks, and tablets. They also aspire that their wireless devices be small with a long battery time and life. To meet the first requirement, a smartphone must support a large number of radio standards; this has motivated the development of Flexible Radios that efficiently support a wide range of wireless communication standards. In this context, adaptive radios modify their performance based on the environment. The Cognitive Radios sense the RF environment to use available spectrum and standards. A key enabling technology for each of these types of radios is Software Defined Radios (SDR) that support numerous current and future standards, share resources between different radio threads, and dynamically add new radio threads to an operational radio. The SDR architecture must also be both area- and energy-efficient. One example of an efficient and flexible baseband architecture is the Scalable Communications Core (SCC), which was developed by Intel Labs and meets many of the requirements for an SDR baseband, including programmability, resource sharing, and efficient scheduling of radio threads. Consisting of a heterogeneous set of coarse-grained, programmable accelerators connected via a packet-based Network-on-Chip (NoC), the resulting architecture is energy- and area-efficient. We taped out a prototype SCC test chip in a 65 nm CMOS process, programmed and validated it for multiple protocols, including WiFi, WiMAX, GPS, Bluetooth, and DVB-H and found that its measured energy and area efficiency were competitive with other flexible baseband architectures.
Anthony Chun, Jeffrey D. Hoffman
Chapter 8. HW/SW Co-design Toolset for Customization of Exposed Datapath Processors
Abstract
Customized processors are an interesting option for implementing software defined radios; they bring benefits of tailored fixed function hardware while adding new advantages such as reduced implementation verification effort and increased post-fabrication flexibility. To reduce the engineering costs and the time-to-market of platforms with new computing devices, the processor customization process should be supported with automated design flows that include tools like retargeting compilers, instruction-set simulators, and RTL generators. This chapter presents an open source processor co-design toolset that is based on a computation resource oriented design methodology where the primary design choices are the set of resources to include in the processor at hand, instead of focusing on instruction encoding details. The toolset is based on a retargetable high-level language compiler and a scalable exposed datapath template which support different styles of parallelism available in applications. In addition to various published academic processor design examples for SDR algorithms, the tools have been used to design and program processors that have been implemented down to silicon layout level and integrated in commercial grade chips.
Pekka Jääskeläinen, Timo Viitanen, Jarmo Takala, Heikki Berg
Chapter 9. FPGA-Based Cognitive Radio Platform with Reconfigurable Front-End and Antenna
Abstract
This chapter presents an FPGA-based SDR platform which serves as a proof-of-concept for cognitive radio techniques. The platform is based on a fully reconfigurable hardware and operates as a 12.8 Mbps RF-to-Ethernet bridge in the Industrial, Scientific, and Medical (ISM) bands of 868 MHz and 2.45 GHz. The data-processing algorithms of the platform are implemented in an FPGA using Xilinx’s System Generator rapid prototyping tool. A MicroBlaze processor is also included to control the dynamic partial reconfiguration of the FPGA for small in-band frequency changes. In order to achieve full-band reconfiguration, a commercial RF front-end and a custom reconfigurable antenna are integrated. Design and implementation details are presented, along with measurement results.
Aitor Arriola, Pedro Manuel Rodríguez, Raúl Torrego, Félix Casado, Zaloa Fernández, Mikel Mendicute, Eñaut Muxika, Juan Ignacio Sancho, Iñaki Val
Chapter 10. Synchronization in NC-OFDM-Based Cognitive Radio Platforms
Abstract
This chapter provides essential information with regard to the synchronization issues in Non-Contiguous Orthogonal Frequency Division Multiplexing (NC-OFDM)-based systems. It also provides a flexible timing synchronization scheme implemented on an Altera Stratix-V Field Programmable Gate Array (FPGA) device. The main component of the synchronizer is a reconfigurable module which calculates the Sum-of-Products (SoP) of the incoming signal with predefined coefficients. The SoP module performs as a multicorrelator on demand. Furthermore, different architectures of the SoP block and their respective performance evaluations are discussed in detail. Eventually, all developed architectures are compared to each other in terms of power consumption, silicon area, maximum frequency, etc.
Farid Shamani, Tapani Ahonen, Jari Nurmi
Chapter 11. Towards Adaptive Cryptography and Security with Software Defined Platforms
Abstract
In this chapter we discuss the challenges for future communication systems, stemming from changing network security environments and the emergence of Internet of Things and sensor networks, all combined with increasing security and privacy requirements. We provide an initial step towards solving these challenges by presenting a design methodology and flow for Software Defined Secure Communications platform, based on our previous TACO platform. With foundations in Transport Triggered Architecture protocol processing applications, the TACO platform is modified by including support to security in the design. We discuss cryptography fundamentals, cryptographic primitives, and adaptive cryptography concepts, and present approaches for their inclusion in the SDSC platform. We discuss briefly a case study of RSA implemented on our platform, and the limited but encouraging results that this study provided. Finally we discuss potential target applications that could benefit from the SDSC platform and design methodology.
Antti Hakkala, Jouni Isoaho, Seppo Virtanen
Chapter 12. The Future of Software-Defined Radio: Recommendations
Abstract
An efficient Software-Defined Radio solution comes when all the aspects of system design are collectively addressed under application specifications and constraints. It includes all—the efforts to design wideband antennas, powerful software to process huge bandwidth of information, optimizations at hardware to maximize performance and nevertheless to mention compilers and operating systems. It is important that every engineer or a scientist working on a particular block of SDR should have a bare-minimum understanding of the entire design stack. There is a need to have clear vision about the targets to be achieved, trade-offs to be made, and a unified approach so that all the objectives are measurable to enable a qualitative and quantitative analysis.
Waqar Hussain, Jouni Isoaho, Jari Nurmi
Backmatter
Metadaten
Titel
Computing Platforms for Software-Defined Radio
herausgegeben von
Waqar Hussain
Jari Nurmi
Jouni Isoaho
Fabio Garzia
Copyright-Jahr
2017
Electronic ISBN
978-3-319-49679-5
Print ISBN
978-3-319-49678-8
DOI
https://doi.org/10.1007/978-3-319-49679-5

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