Conclusions

In the previous chapters we have considered testing, design for testability and self-checking design of combinational static and dynamic CMOS circuits. Not much work has been done in the area of test generation for sequential CMOS circuits. Owing to the difficult and time-consuming nature of sequential circuit testing, usually only the stuck-at fault model is assumed even for CMOS circuits. In order to reduce the complexity of sequential circuit testing, design for testability techniques, such as scan techniques, are used. These techniques reduce the complexity of test generation to that of testing combinational circuits. For example, in the scan path technique [WILL73], the circuit has a normal mode of operation and a test mode. In the test mode the circuit flip-flops are interconnected to form a shift register (i.e. the scan path). It is easy to test such a scan path. The test patterns for the combinational part of the circuit are serially shifted in and the responses are serially shifted out through the flip-flops. A scan path technique called level-sensitive scan design (LSSD) was developed for latch-based systems [EICH77], and is extensively used in IBM. Some chip area penalty has to be paid to incorporate these design for testability features into the chip.