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Erschienen in:
Challenges and Opportunities in VLSI for Systems Dependability Kapitel lesen Erstes Kapitel lesen

2019 | OriginalPaper | Buchkapitel

8. Connectivity in Electronic Packaging

verfasst von : Hiroki Ishikuro, Tadahiro Kuroda, Atsutake Kosuge, Mitsumasa Koyanagi, Kang Wook Lee, Hiroyuki Hashimoto, Makoto Motoyoshi

Erschienen in: VLSI Design and Test for Systems Dependability

Verlag: Springer Japan

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Abstract

This chapter deals with the issue of packaging and interconnects in electronic systems. An electronic system in general consists of multiple subsystem modules in certain form of packages and electrical interconnects between them. A module, in turn, consists of multiple VLSI chips and interconnects. Interconnects often become bottleneck of the performance of electronic systems because the performance gap between the bus bandwidth and processor core speed has increased as the process technology scales. Development in the performance of systems has thus been accompanied by the development of interconnects as well as VLSI chips. Exactly like what happened in the VLSI, the technology of packaging and interconnects has developed tremendously in terms of bandwidths, power dissipation, form factors (physical dimensions), and so forth. In fact, it has always been one of the central issues in the design of systems, involved sophisticated engineering, and required attention from the perspective of dependability. Section 8.1 gives an overview of the requirements for packaging and interconnects and highlights wireless technology for packaging as an emerging technology for packaging or integrating complex systems. Section 8.2 introduces wireless interconnect and compares it with conventional wired interconnect in a few practical examples. Section 8.3 describes the through-silicon via (TSV) in three-dimensional (3D) integration of silicon VLSI from the perspective of performance and dependability and introduces the concept of redundant vias.

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Vorheriges Kapitel Connectivity in Wireless Telecommunications
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Metadaten
Titel
Connectivity in Electronic Packaging
verfasst von
Hiroki Ishikuro
Tadahiro Kuroda
Atsutake Kosuge
Mitsumasa Koyanagi
Kang Wook Lee
Hiroyuki Hashimoto
Makoto Motoyoshi
Copyright-Jahr
2019
Verlag
Springer Japan
Buch
VLSI Design and Test for Systems Dependability

Print ISBN: 978-4-431-56592-5

Electronic ISBN: 978-4-431-56594-9

Copyright-Jahr: 2019

DOI
https://doi.org/10.1007/978-4-431-56594-9_8

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