Constraining Designs for Synthesis and Timing Analysis

Frontmatter

Chapter 1. Introduction

Abstract

Application-specific integrated circuit (ASIC) is an IC targeted for a specific application, e.g., chips designed to run graphics on a game console, standard interfaces like USB, PCI bus to consumer electronics, special functions to control automotive electronics, and chips for smart phones. In the early days of chip design, ASICs were a few thousand gates. With advancements in deep submicron technology, today’s ASICs run into millions of gates. Today, some of the more complex ASICs combine processors, memory blocks, and other ASIC or ASIC derivatives called IPs (intellectual property). These are called SoCs or system on a chip. The reality is today’s SoCs will become the blocks or IPs for the future SoC design. This complex nature of ASIC development requires a well-structured design flow that is scalable and provides enough flexibility to designers and SoC integrators alike to define a methodology for seamless design.

Sridhar Gangadharan, Sanjay Churiwala

Chapter 2. Synthesis Basics

Abstract

Synthesis is the first step in the design process, where timing constraints are used.

Sridhar Gangadharan, Sanjay Churiwala

Chapter 3. Timing Analysis and Constraints

Abstract

Before we learn to constrain our design, let us first understand the basics of timing analysis. Fundamentally, timing analysis is of two kinds:

Sridhar Gangadharan, Sanjay Churiwala

Chapter 4. SDC Extensions Through Tcl

Abstract

The term “Synopsys Design Constraints” (aka SDC) is used to describe design requirements for timing, power, and area and is the most commonly used format by EDA tools used for synthesis, static timing analysis, and place and route. This chapter provides a brief history of timing constraints and an overview of the SDC language.

Sridhar Gangadharan, Sanjay Churiwala

Chapter 5. Clocks

Abstract

A synchronous design is one where a control signal triggers the circuit to transition from one state to another. Such a trigger can happen at the positive or negative edge or both edges of the control signal. At the appropriate trigger edge, which may be active high or active low, input, outputs, internal registers, and nodes reach a stable state. Such a control signal which acts as a trigger for a synchronous design is called a clock and the edge on which the design triggers is called the active edge of the clock. A circuit that generates such a clock signal is called a clock generator.

Sridhar Gangadharan, Sanjay Churiwala

Chapter 6. Generated Clocks

Abstract

Most complex designs require more than one clock for its functioning. When there are multiple clocks in a design, they would need to interact or share a relationship. Asynchronous clocks are clock signals that don’t share a fixed phase relationship. Having only asynchronous clocks in the design makes it really hard to meet setup and hold requirements when multiple clock domains are interacting. We will explain about this in Chap. 7 as to why it is so. Synchronous clocks share a fixed phase relationship. More often than not synchronous clocks originate from the same source.

Sridhar Gangadharan, Sanjay Churiwala

Chapter 7. Clock Groups

Abstract

When a design has more than one clock, the timing of such a design depends not just on the frequency of clocks but also on the relation the clocks share with each other. Synchronous clocks are clocks which share a deterministic phase relationship. More often than not, synchronous clocks share the same source.

Sridhar Gangadharan, Sanjay Churiwala

Chapter 8. Other Clock Characteristics

Abstract

In the preceding chapters, we assumed the clock to be ideal, i.e., they transition from 0 to 1 and vice versa instantaneously (have a rectangular waveform); they reach all the flops in the design at the same time (all edges align) and there is no delay between the clock generation circuit and the place where the clock is actually consumed. In reality, clocks are never ideal.

Sridhar Gangadharan, Sanjay Churiwala

Chapter 9. Port Delays

Abstract

Once the clock constraints have been applied, all the register to register paths can be timed. Now, the delay constraints have to be applied on non-clock ports. If input and output port constraints are not specified, timing analysis tools assume a highly optimistic timing requirements on the interfaces. They assume the combinational logic inside the block can have the entire period to itself and leave nothing for the portion of the signal outside the block.

Sridhar Gangadharan, Sanjay Churiwala

Chapter 10. Completing Port Constraints

Abstract

The delay through a specific cell depends on the slew/transition rate at its input as well as the load that it sees at its output. For cells inside the design, the fanin driver and the fanout cone is also part of the design. So the transition rate as well as the load can be computed by the tool. However, for the cells which are being driven by the input port, the input transition time is not known. Similarly, for the cells which drive the output port, the load is not known. Thus, designers need to provide the input transition time for the input signals and the external load that the output port will see. If not specified, the transition time is assumed to be 0 namely, a sharp ramp (equivalent to infinite drive strength), and load is assumed to be 0 namely, no external load. Both these conditions are highly optimistic.

Sridhar Gangadharan, Sanjay Churiwala

Chapter 11. False Paths

Abstract

So far we saw how you can constrain your clocks and ports to specify the timing requirements for the design. However, even after setting these global requirements, designers would want to make certain exclusions for certain paths. This may be done to specify certain unique requirements on the paths or provide additional scope for leniency. Such constraints are referred to as timing exceptions. There are three kinds of timing exceptions:

Sridhar Gangadharan, Sanjay Churiwala

Chapter 12. Multi Cycle Paths

Abstract

By default, each path is timed for a single cycle, i.e., data launched at any edge of the clock should be captured by the next flop at the next rising edge of the clock on the destination flop. Figure 12.1 shows this relationship.

Sridhar Gangadharan, Sanjay Churiwala

Chapter 13. Combinational Paths

Abstract

Usually, outputs are always registered—just before being presented to the port. In many cases, inputs are also registered immediately after entering the block. In any case, most of the times, each signal entering an input gets registered at least once, before it comes out through an output port.

Sridhar Gangadharan, Sanjay Churiwala

Chapter 14. Modal Analysis

Abstract

Today’s designs are very complex. They are “System on a Chip” in the real sense. The same chip performs multiple functions at different points of time. Within the chip also, there are portions in the design which behave one way in one use mode and behave differently in another use mode.

Sridhar Gangadharan, Sanjay Churiwala

Chapter 15. Managing Your Constraints

Abstract

As the complexity of designs increases there is a need to accurately model timing constraints for early design closure. When done correctly, they help not only to achieve faster timing closure but also reduce iterations between front-end and back-end teams. In reality constraints are constantly being tweaked as the design is being pushed from RTL to post layout. This requires the design to be partitioned appropriately and the constraints to be managed effectively so that the design intent is preserved at every step.

Sridhar Gangadharan, Sanjay Churiwala

Chapter 16. Miscellaneous SDC Commands

Abstract

In this chapter, we deal with some additional SDC commands and concepts.

Sridhar Gangadharan, Sanjay Churiwala

Chapter 17. XDC: Xilinx Extensions to SDC

Abstract

FPGA design flows have become very similar to ASIC flow. They both usually start from RTL and require a number of similar physical and timing constraints in order to ensure proper functionality and timing on hardware. Adoption of industry standards has also helped with the convergence between the two worlds, particularly on the timing constraints side via the adoption of SDC and deprecation of proprietary equivalent formats. The main differences remain around the rules to be followed during the design implementation. ASICs come with an extensive set of manufacturability and testability rules, while FPGA designs need to follow a set of higher level rules such as device capacity and architecture features compatibility. These differences are reflected in the FPGA design flow where the tools are able to simplify or hide a number of complex rules that are typically encountered in ASIC flows, for example on signal integrity, and automatically create some constraints such as generated clocks or jitter. The following chapter will focus on how SDC support has been extended in Xilinx new generation of FPGA compilation software. The Xilinx extension to SDC is called XDC.

Sridhar Gangadharan, Sanjay Churiwala, Frederic Revenu

Backmatter