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Über dieses Buch

This book provides readers with a comprehensive overview of the state-of-the-art in optical contactless probing approaches, in order to fill a gap in the literature on VLSI Testing. The author highlights the inherent difficulties encountered with the mechanical probe and testability design approaches for functional and internal fault testing and shows how contactless testing might resolve many of the challenges associated with conventional mechanical wafer testing. The techniques described in this book address the increasing demands for internal access of the logic state of a node within a chip under test.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Conventional Test Methods

Abstract
With shrinking sizes of devices and increasing chip densities, circuits have become so fast, compact, and inaccessible that the use of conventional methods based on mechanical probe has become limited and inadequate. The conventional test methods or the mechanical probe techniques used for functional and internal fault testing face increasingly difficult challenges. This chapter discusses these limitations of conventional methods and highlights the importance of alternative probing solutions to address the upcoming challenges.
Selahattin Sayil

Chapter 2. Testability Design

Abstract
Testability design or design for testability (DFT) implies adding circuits within a test object to make it easier to test. With advances in VLSI, it is basically the increasing inaccessibility of the internal circuits that makes testing more and more difficult and causes testing costs to be an ever-growing portion of a product’s total costs. DFT techniques are valuable methods for helping solve the growing test problem. The cost is the increased silicon circuit area to accommodate the hardware overhead and potentially reduced circuit performance.
Selahattin Sayil

Chapter 3. Other Techniques Based on the Contacting Probe

Abstract
As technology scaling continues, chip testing becomes more complex and challenging. Testing techniques in general can be grouped as functional and structural or defect-based testing techniques. A functional test applies predetermined set of patterns at the inputs of an integrated circuit and compares to the expected responses. The goal is to verify the functionality of the chip under test. Structural tests, on the other hand, target on the defect detection using circuit structure. These may include tests based on stuck-at faults, delay tests, and tests based on quiescent current (IDDQ) and transient current (IDDT) detection. This chapter covers IDDQ and IDDT test methods adopted by industry and discusses on shortcomings. The remainder of this chapter describes photoconductive sampling probe (PC probe). PC probe uses laser beam to activate test inputs and to sample test outputs and nonetheless requires a hard probe to make contact with the metallization line. Since it is clearly not a contactless testing approach, this method is covered in this chapter.
Selahattin Sayil

Chapter 4. Contactless Testing

Abstract
With continuous miniaturization of devices and increasing chip densities, conventional mechanical probe approach used for internal fault detection and functional circuit testing faces increasing challenges. Conventional probes have their limitations due to their large size and inherent parasitic effects. In addition, large chip I/O pad counts challenge testing reliability in numerous ways. Contactless testing and diagnostic measurement methods might resolve many of the challenges associated with conventional mechanical wafer testing. These nonmechanical techniques can be very useful for debugging and design verification, as well as for functional testing. After some introduction on contactless testing, this chapter focuses on the photoexcitation probe technique. This technique uses a focused laser beam to photoexcite carriers near an active device to detect logic levels of transistors.
Selahattin Sayil

Chapter 5. Electron Beam and Photoemission Probing

Abstract
Electron beam testing (EBT) is the most widely used contactless probing technique for internal timing characterization and for diagnostic of digital integrated circuits. This technique uses an electron beam to stimulate secondary electron emission from metallized surfaces. It uses the energy distribution function of the released secondary electrons which is in turn a function of the voltage at the test point. A very attractive feature of EBT is the quick and easy positioning of the electron beam probe and the possibility of making micrographs at any desired location in short time. It is the most industrially developed contactless testing technique. The photoemissive probe, on the other hand, uses a pulsed optical beam of a certain energy to probe a signal on a metal line of any substrate. The optical beam causes photoelectrons to be emitted from the top layer of a metal from which the waveform of the signal is derived.
Selahattin Sayil

Chapter 6. Electro-Optic Sampling and Charge-Density Probe

Abstract
Electro-optic sampling is among the fastest of the current optical techniques available. This technique is based on the “Pockels effect” where the optical properties of a crystal change according to an applied electric field applied across it. By sending the light through the crystal, measuring the polar polarization changed, unknown test-point voltages can be determined. There are two general techniques for electro-optic sampling, namely, the external and the internal electro-optic (e-o) sampling. The external electro-optic method uses a small electro-optic crystal as the electro-optic medium, while the internal electro-optic technique uses the circuit substrate itself as the electro-optic medium. In another optical technique named “charge-density” probing, the plasma-optical effect is utilized where charge-density modulations within devices and parasitic PN junctions cause local refractive index changes. By interferometrically sensing these refractive index variations from the backside of an IC, these measurements can be related to either a current or a voltage signal.
Selahattin Sayil

Chapter 7. Electric Force Microscope, Capacitive Coupling, and Scanning Magnetoresistive Probe

Abstract
Electric force microscope (EFM) testing is based on Coulombic force interactions between an EFM probe and a test point. An electric signal on an interconnected line creates an electric force between the tip and the device under test which causes a detectable bending of the cantilever. This bending amount is optically detected and electrically analyzed by a lock-in amplifier. In capacitive coupling method, an electrode is placed in close proximity to a pad on the wafer. The voltage transients on the pad induce weak displacement currents on the electrode. This effect can be used to detect electrical pulses propagating through an IC. For current measurements, scanning magnetoresistive probe has also been suggested to detect currents in a contactless manner.
Selahattin Sayil

Chapter 8. Probing Techniques Based on Light Emission from Chip

Abstract
Various contactless testing methodologies have been proposed to resolve many of the challenges associated with conventional mechanical wafer testing. Most of these methods offered, however, suffer from at least one of the limitations. For example, electron beam and photoemissive probe techniques suffer from the high equipment cost, the complex preparation steps, and logic bandwidth measurement limitations. Other techniques have limitations such as damaging risk, material limitations, and crosstalk. Therefore, researchers have sought alternative contactless methods such as the ones based on chip light emission. In the picosecond imaging circuit analysis or PICA technique, light pulses emitted by CMOS transistors in saturation during the switching events of individual gates are collected. The technique can detect timing-related defects in modern VLSI circuits. The LEOSCL (light emission from off-state leakage) technique observes the near-infrared light emission associated with the off-state leakage of transistor. Since the emission is brighter for an NMOS transistor compared to a PMOS, this information is used to detect logic states. Finally, a technique based on the integration of a silicon light emitter and a silicon photodiode on the device under test has been proposed to address the growing test problem. The uniqueness of this proposed method lies in the fact that it is fully an optical technique utilizing visible light and is completely compatible with standard silicon IC processing.
Selahattin Sayil

Chapter 9. All-Silicon Optical Technology for Contactless Testing of Integrated Circuits

Abstract
The uniqueness of the “all-silicon optical testing methodology” lies in the fact that it is fully an optical technique utilizing visible light, and it is completely compatible with standard silicon IC processing. It uses optical signals transmitted to the circuit for “inputting” the stimulus data and also uses optical signals from the circuit for observation of the logic output. In addition, this approach is fully compatible with the simultaneous use of mechanical probes for power and other signals. The approach avoids many of the limitations of other contactless techniques.
Selahattin Sayil

Chapter 10. Comparison of Contactless Testing Methodologies

Abstract
An ideal contactless probing system would be relatively easy, inexpensive to operate, and compatible with the existing test equipment. It would not cause any perturbation on the circuit under test and would measure electric signals with minimum cross talk. The bandwidth of the test system for logic signals would be in GHz region, and the method would not be limited to certain materials. This chapter presents a review of state-of-the-art contactless testing methodologies that covered in this text and makes a comparison based on above properties. This will be valuable to readers as contactless probing is gaining more importance as fabrication technologies become smaller and more susceptible to the parasitic impact of mechanical probes.
Selahattin Sayil
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