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Erschienen in:
Introduction Kapitel lesen Erstes Kapitel lesen

2014 | OriginalPaper | Buchkapitel

3. Continuous-Time Delta-Sigma Modulators at High Sampling Rates

verfasst von : Muhammed Bolatkale, Lucien J. Breems, Kofi A. A. Makinwa

Erschienen in: High Speed and Wide Bandwidth Delta-Sigma ADCs

Verlag: Springer International Publishing

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Abstract

This chapter describes the design of a continuous-time delta-sigma (CTΔΣ) modulator that can achieve a 125 MHz signal bandwidth (BW) with a 70 dB dynamic range (DR) in 45 nm CMOS. As explained in the previous chapter, various system-level non-idealities (noise, non-linearity, metastability and excess loop delay (ELD)), will limit its performance. Especially for a modulator which targets a wide bandwidth, these limitations pose a major challenge.

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Vorheriges Kapitel Continuous-Time Delta-Sigma Modulator
Nächstes Kapitel A 4 GHz Continuous-Time ΔΣ ADC
Fußnoten
1
MASH \(\Delta \Sigma \) modulators offer another route to increase signal BW [7]. However, the total output signal BW still depends on the signal BW of a single-loop modulator. Although this work focuses on extending the signal BW of a single-order modulator, the results can also be applied to increase the signal BW of MASH modulators.
 
2
CLK Q signal in Fig. 3.27b and RST signal in Fig. 4.​4 represent the same signal.
 
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Metadaten
Titel
Continuous-Time Delta-Sigma Modulators at High Sampling Rates
verfasst von
Muhammed Bolatkale
Lucien J. Breems
Kofi A. A. Makinwa
Copyright-Jahr
2014
Buch
High Speed and Wide Bandwidth Delta-Sigma ADCs

Print ISBN: 978-3-319-05839-9

Electronic ISBN: 978-3-319-05840-5

Copyright-Jahr: 2014

DOI
https://doi.org/10.1007/978-3-319-05840-5_3

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