Skip to main content
Erschienen in: Journal of Electronic Testing 3/2022

30.06.2022

Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs

verfasst von: Trevor Kroeger, Wei Cheng, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi

Erschienen in: Journal of Electronic Testing | Ausgabe 3/2022

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

The hardware primitives known as Physically Unclonable Functions (PUFs) generate unique signatures based on uncontrollable variations which occur during the manufacturing process of silicon chips. These signatures are in turn used for securing Integrated Circuits either as a secret key for cryptographic modules, or as a medium for authenticating devices. Naturally being a security primitive, PUFs are the target for attacks as such it is important to mitigate such vulnerabilities. This paper in particular investigates PUFs’ vulnerability to power-based modeling attacks. Here, we expand upon our previous simulation based Cross-PUF attacks by targeting PUFs realized in real-silicon; namely, we consider PUFs deployed in Field-Programmable Gate Array (FPGA) fabrics. In Cross-PUF attacks, a model of a reference PUF is used to attack another PUF realized from the same HSPICE simulated design or the same bitstream in FPGA. We also investigate the impact of such attacks on multi-bit parallel PUFs. The HSPICE simulation results are compared vis-a-vis with the FPGA implementation outcome of these attacks confirming the effectiveness of such simulations. Finally we show that a combination of Dual Rail logic and Random Initialization logic, named DRILL, can be effectively used to thwart such power-based modeling attacks.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Weitere Produktempfehlungen anzeigen
Fußnoten
1
For the sake of brevity, we omitted the experimental results of another two algorithms, namely Decision Tree and Random Forest, since SVM provides a higher accuracy than that of those two.
 
Literatur
2.
Zurück zum Zitat Anusha G, Kumar A, Kandpal K (2020) A fully on-chip low-dropout regulator for SoC applications. Procedia Comput Sci 171:1009–1017CrossRef Anusha G, Kumar A, Kandpal K (2020) A fully on-chip low-dropout regulator for SoC applications. Procedia Comput Sci 171:1009–1017CrossRef
4.
Zurück zum Zitat Becker GT, Kumar R (2014) Active and passive side-channel attacks on delay based PUF designs. International Association for Cryptologic Research Cryptology Archive p 287 Becker GT, Kumar R (2014) Active and passive side-channel attacks on delay based PUF designs. International Association for Cryptologic Research Cryptology Archive p 287
5.
Zurück zum Zitat Becker GT (2015) The gap between promise and reality: On the insecurity of XOR arbiter PUFs. In: Proc. International Workshop on Cryptographic Hardware and Embedded Systems. Springer, pp 535–555 Becker GT (2015) The gap between promise and reality: On the insecurity of XOR arbiter PUFs. In: Proc. International Workshop on Cryptographic Hardware and Embedded Systems. Springer, pp 535–555
6.
Zurück zum Zitat Bruneau N, Danger JL, Facon A, Guilley S, Hamaguchi S, Hori Y, Kang Y, Schaub A (2018) Development of the unified security requirements of PUFs during the standardization process. In: Proc. International Conference on Security for Information Technology and Communications. Springer, pp 314–330 Bruneau N, Danger JL, Facon A, Guilley S, Hamaguchi S, Hori Y, Kang Y, Schaub A (2018) Development of the unified security requirements of PUFs during the standardization process. In: Proc. International Conference on Security for Information Technology and Communications. Springer, pp 314–330
7.
Zurück zum Zitat Chatterjee D, Mukhopadhyay D, Hazra A (2020) Interpose PUF can be PAC Learned. International Association for Cryptologic Research Cryptology ePrint Archive p 471 Chatterjee D, Mukhopadhyay D, Hazra A (2020) Interpose PUF can be PAC Learned. International Association for Cryptologic Research Cryptology ePrint Archive p 471
8.
Zurück zum Zitat Cherif Z, Danger J-L, Guilley S, Bossuet L (2012) An easy-to-design PUF based on a single oscillator: the loop PUF. In: Proc. 15th Euromicro Conference on Digital System Design, pp 156–162 Cherif Z, Danger J-L, Guilley S, Bossuet L (2012) An easy-to-design PUF based on a single oscillator: the loop PUF. In: Proc. 15th Euromicro Conference on Digital System Design, pp 156–162
9.
Zurück zum Zitat Delvaux J, Verbauwhede I (2013) Side channel modeling attacks on 65 nm arbiter PUFs exploiting CMOS device noise. In: Proc. Int’l Symp. on Hardware-Oriented Security and Trust (HOST), pp 137–142 Delvaux J, Verbauwhede I (2013) Side channel modeling attacks on 65 nm arbiter PUFs exploiting CMOS device noise. In: Proc. Int’l Symp. on Hardware-Oriented Security and Trust (HOST), pp 137–142
10.
Zurück zum Zitat Ebrahimabadi M, Younis M, Karimi N (2022) A puf-based modeling-attack resilient authentication protocol for IoT devices. IEEE Internet Things J 9(5):3684–3703CrossRef Ebrahimabadi M, Younis M, Karimi N (2022) A puf-based modeling-attack resilient authentication protocol for IoT devices. IEEE Internet Things J 9(5):3684–3703CrossRef
12.
Zurück zum Zitat Fukushima K et al (2016) Delay PUF assessment method based on side-channel and modeling analyzes: The final piece of all-in-one assessment methodology. In: IEEE Trustcom/BigDataSE/ISPA, pp 201–207 Fukushima K et al (2016) Delay PUF assessment method based on side-channel and modeling analyzes: The final piece of all-in-one assessment methodology. In: IEEE Trustcom/BigDataSE/ISPA, pp 201–207
14.
Zurück zum Zitat Gassend B, Clarke D, van Dijk M, Devadas S (2002) Silicon physical random functions. In: Proc. ACM Conference on Computer and Communications Security, pp 148–160 Gassend B, Clarke D, van Dijk M, Devadas S (2002) Silicon physical random functions. In: Proc. ACM Conference on Computer and Communications Security, pp 148–160
16.
Zurück zum Zitat Herder C, Yu M, Koushanfar F, Devadas S (2014) Physical unclonable functions and applications: A tutorial. Proc IEEE 102(8):1126–1141CrossRef Herder C, Yu M, Koushanfar F, Devadas S (2014) Physical unclonable functions and applications: A tutorial. Proc IEEE 102(8):1126–1141CrossRef
18.
Zurück zum Zitat Jiang Q, Zhang X, Zhang N, Tian Y, Ma X, Ma JQ (2019) Two-factor authentication protocol using physical unclonable function for IoV. In: Proc. IEEE/CIC International Conference on Communications in China (ICCC), pp 195–200 Jiang Q, Zhang X, Zhang N, Tian Y, Ma X, Ma JQ (2019) Two-factor authentication protocol using physical unclonable function for IoV. In: Proc. IEEE/CIC International Conference on Communications in China (ICCC), pp 195–200
19.
Zurück zum Zitat Karimi N, Danger J-L, Guilley S (2018) Impact of aging on the reliability of delay PUFs. J Electron Test: Theory Appl 34(5):571–586CrossRef Karimi N, Danger J-L, Guilley S (2018) Impact of aging on the reliability of delay PUFs. J Electron Test: Theory Appl 34(5):571–586CrossRef
20.
Zurück zum Zitat Kim SJ (2021) Integrated and Distributed Digital Low-Drop-Out Regulators with Event-Driven Controls and Side-Channel Attack Resistance. Columbia University Kim SJ (2021) Integrated and Distributed Digital Low-Drop-Out Regulators with Event-Driven Controls and Side-Channel Attack Resistance. Columbia University
21.
Zurück zum Zitat Koushanfar F (2011) Integrated circuits metering for piracy protection and digital rights management: An overview. In: Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI, Association for Computing Machinery, New York, NY, USA, p 449–454. https://doi.org/10.1145/1973009.1973110 Koushanfar F (2011) Integrated circuits metering for piracy protection and digital rights management: An overview. In: Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI, Association for Computing Machinery, New York, NY, USA, p 449–454. https://​doi.​org/​10.​1145/​1973009.​1973110
22.
Zurück zum Zitat Kroeger T, Cheng W, Guilley S, Danger J-L, Karimi N (2020) Cross-PUF attacks on arbiter-PUFs through their power side-channel. In: Proc. IEEE International Test Conference (ITC), pp 1–5 Kroeger T, Cheng W, Guilley S, Danger J-L, Karimi N (2020) Cross-PUF attacks on arbiter-PUFs through their power side-channel. In: Proc. IEEE International Test Conference (ITC), pp 1–5
23.
Zurück zum Zitat Kroeger T, Cheng W, Guilley S, Danger J-L, Karimi N (2021) Enhancing the resiliency of multi-bit parallel arbiter-PUF and its derivatives against power attacks. In: Bhasin S, De Santis F (eds) Constructive side-channel analysis and secure design. COSADE 2021. Lecture notes in computer science, vol 12910, pp 303–321 Kroeger T, Cheng W, Guilley S, Danger J-L, Karimi N (2021) Enhancing the resiliency of multi-bit parallel arbiter-PUF and its derivatives against power attacks. In: Bhasin S, De Santis F (eds) Constructive side-channel analysis and secure design. COSADE 2021. Lecture notes in computer science, vol 12910, pp 303–321
24.
Zurück zum Zitat Kroeger T, Cheng W, Guilley S, Danger JL, Karimi N (2021) Making obfuscated PUFs secure against power side-channel based modeling attacks. In: Proc. Design Automation and Test Europe (DATE) Kroeger T, Cheng W, Guilley S, Danger JL, Karimi N (2021) Making obfuscated PUFs secure against power side-channel based modeling attacks. In: Proc. Design Automation and Test Europe (DATE)
27.
Zurück zum Zitat Mahmoud A, Rührmair U, Majzoobi M, Koushanfar F (2013) Combined modeling and side channel attacks on strong PUFs. International Association for Cryptologic Research Cryptology ePrint Archive 2013:632 Mahmoud A, Rührmair U, Majzoobi M, Koushanfar F (2013) Combined modeling and side channel attacks on strong PUFs. International Association for Cryptologic Research Cryptology ePrint Archive 2013:632
28.
Zurück zum Zitat Mangard S, Oswald E, Popp T (2006) Power Analysis Attacks: Revealing the Secrets of Smart Cards. Springer Mangard S, Oswald E, Popp T (2006) Power Analysis Attacks: Revealing the Secrets of Smart Cards. Springer
29.
Zurück zum Zitat Maiti A, Gunreddy V, Schaumont P (2013) A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions. Springer, New York, New York, NY, pp 245–267 Maiti A, Gunreddy V, Schaumont P (2013) A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions. Springer, New York, New York, NY, pp 245–267
30.
Zurück zum Zitat Majzoobi M, Koushanfar F, Devadas S (2010) FPGA PUF using programmable delay lines. In: Proc. IEEE Int’l Workshop on Information Forensics and Security, pp 1–6 Majzoobi M, Koushanfar F, Devadas S (2010) FPGA PUF using programmable delay lines. In: Proc. IEEE Int’l Workshop on Information Forensics and Security, pp 1–6
31.
Zurück zum Zitat Mars A, Adi W (2018) New Concept for Physically-Secured E-Coins Circulations. In: Adaptive Hardware and Systems, pp 333–338 Mars A, Adi W (2018) New Concept for Physically-Secured E-Coins Circulations. In: Adaptive Hardware and Systems, pp 333–338
32.
Zurück zum Zitat Nagata M, Miki T, Miura N (2022) Physical attack protection techniques for ic chip level hardware security. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30(1):5–14 Nagata M, Miki T, Miura N (2022) Physical attack protection techniques for ic chip level hardware security. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30(1):5–14
34.
Zurück zum Zitat Nguyen PH et al (2019) The Interpose PUF: Secure PUF Design against State-of-the-art Machine Learning Attacks. Trans on Cryptographic Hardware and Embedded Systems (CHES) p 243–290 Nguyen PH et al (2019) The Interpose PUF: Secure PUF Design against State-of-the-art Machine Learning Attacks. Trans on Cryptographic Hardware and Embedded Systems (CHES) p 243–290
36.
Zurück zum Zitat Rührmair U et al (2010) Modeling Attacks on Physical Unclonable Functions. In: ACM Conference on Computer and Communications Security, pp 237–249 Rührmair U et al (2010) Modeling Attacks on Physical Unclonable Functions. In: ACM Conference on Computer and Communications Security, pp 237–249
37.
Zurück zum Zitat Rührmair U, Sölter J (2014) PUF modeling attacks: An introduction and overview. In: Proc. Design Automation and Test Europe (DATE), pp 1–6 Rührmair U, Sölter J (2014) PUF modeling attacks: An introduction and overview. In: Proc. Design Automation and Test Europe (DATE), pp 1–6
38.
Zurück zum Zitat Rührmair U, Xu X, Sölter J, Mahmoud A, Majzoobi M, Koushanfar F, Burleson W (2014) Efficient power and timing side channels for physical unclonable functions. In: Batina L, Robshaw M (eds) Cryptographic hardware and embedded systems – CHES 2014. Lecture notes in computer science, vol 8731. Springer, pp 476–492 Rührmair U, Xu X, Sölter J, Mahmoud A, Majzoobi M, Koushanfar F, Burleson W (2014) Efficient power and timing side channels for physical unclonable functions. In: Batina L, Robshaw M (eds) Cryptographic hardware and embedded systems – CHES 2014. Lecture notes in computer science, vol 8731. Springer, pp 476–492
39.
Zurück zum Zitat Santikellur P, Bhattacharyay A, Chakraborty RS (2019) Deep learning based model building attacks on arbiter PUF compositions. Cryptology ePrint Archive Santikellur P, Bhattacharyay A, Chakraborty RS (2019) Deep learning based model building attacks on arbiter PUF compositions. Cryptology ePrint Archive
40.
Zurück zum Zitat Soybali M, Ors B, Saldamli G (2011) Implementation of a PUF circuit on a FPGA. In: Proc. International Conference on New Technologies, Mobility and Security, pp 1–5 Soybali M, Ors B, Saldamli G (2011) Implementation of a PUF circuit on a FPGA. In: Proc. International Conference on New Technologies, Mobility and Security, pp 1–5
42.
Zurück zum Zitat Tebelmann L, Danger JL, Pehl M (2020) Self-secured PUF: protecting the loop PUF by masking. Constructive Side-Channel Analysis and Secure Design (COSADE) 12244:293–314CrossRef Tebelmann L, Danger JL, Pehl M (2020) Self-secured PUF: protecting the loop PUF by masking. Constructive Side-Channel Analysis and Secure Design (COSADE) 12244:293–314CrossRef
43.
Zurück zum Zitat Wisiol N, Mühl C, Pirnay N, Nguyen PH, Margraf M, Seifert J-P, van Dijk M, Rührmair U (2020) Splitting the interpose PUF: A novel modeling attack strategy. Trans on Cryptographic Hardware and Embedded Systems (CHES) 3:97–120CrossRef Wisiol N, Mühl C, Pirnay N, Nguyen PH, Margraf M, Seifert J-P, van Dijk M, Rührmair U (2020) Splitting the interpose PUF: A novel modeling attack strategy. Trans on Cryptographic Hardware and Embedded Systems (CHES) 3:97–120CrossRef
45.
Zurück zum Zitat Yu W, Uzun OA, Köse S (2015) Leveraging on-chip voltage regulators as a countermeasure against side-channel attacks. In: Proc. 52nd Annual Design Automation Conf., ACM, pp 1–6 Yu W, Uzun OA, Köse S (2015) Leveraging on-chip voltage regulators as a countermeasure against side-channel attacks. In: Proc. 52nd Annual Design Automation Conf., ACM, pp 1–6
Metadaten
Titel
Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs
verfasst von
Trevor Kroeger
Wei Cheng
Jean-Luc Danger
Sylvain Guilley
Naghmeh Karimi
Publikationsdatum
30.06.2022
Verlag
Springer US
Erschienen in
Journal of Electronic Testing / Ausgabe 3/2022
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-022-06012-z

Weitere Artikel der Ausgabe 3/2022

Journal of Electronic Testing 3/2022 Zur Ausgabe

EditorialNotes

Editorial