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This book was motivated by the problems being faced with shrinking IC process feature sizes. It is well known that as process feature sizes shrink, a host of electrical problems like cross-talk, electromigration, self-heat, etc. are becoming important. Cross-talk is one of the major problems since it results in unpredictable design behavior. In particular, it can result in significant delay variation or signal integrity problems in a wire, depending on the state of its neighboring wires. Typical approaches to tackle the cross-talk problem attempt to fix the problem once it is created. In our approach, we ensure that cross-talk is eliminated by design. The work described in this book attempts to take an "outside-the-box" view and propose a radically different design style. This design style first imposes a fixed layout pattern (or fabric) on the integrated circuit, and then embeds the circuit being implemented into this fabric. The fabric is chosen carefully in order to eliminate the cross-talk problem being faced in modem IC processes. With our choice of fabric, cross-talk between adjacent wires on an IC is reduced by between one and two orders of magnitude. In this way, the fabric concept eliminates cross-talk up-front, and by design. We propose two separate design flows, each of which uses the fabric concept to implement logic. The first flow uses fabric-compliant standard cells as an im­ plementation vehicle. We call these cells fabric cells, and they have the same logic functionality as existing standard cells with which they are compared.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

Abstract
With the rapid development of VLSI fabrication technologies, we have reached an era where the minimum feature sizes of the leading processes is well below 1 εm. Such processes are called Deep Sub-Micron (DSM) processes. With shrinking feature sizes, many new problems arise. Certain electrical problems like cross-talk, electromigration, self-heat and statistical processing variations are becoming increasingly important. Until recently, IC designers were able to cleanly partition the design task into a logical and a physical one, with no interaction between the two sub-tasks. The increasing importance of the above electrical effects requires that designers consider the interaction between logical and physical design at the same time. This makes the design task more complex and time-consuming.
Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Chapter 2. Validating Deep Sub-Micron Effects

Abstract
In this chapter, we motivate our approach by a brief analysis on the trends of resistance and capacitance of on-chip interconnect with decreasing feature sizes of VLSI ICs (which is described in Section 2). We show analytically that the capacitance of a conductor to its neighboring conductors is becoming an increasing fraction of its total capacitance, thus giving rise to a situation where cross-talk problems become increasingly important. In Section 3, we detail our interconnect geometry predictions. Based on these predictions, we experimentally validate the above capacitance trends in Section 4. Finally, in Sections 5, we experimentally validate the delay variation (Section 5.1) and signal integrity (Section 5.2) problems by means of SPICE [Nagel, 1995] simulations. In Section 6, we review some existing techniques to handle cross-talk.
Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Chapter 3. VLSI Layout Fabrics

Abstract
In a typical VLSI IC, the preferred routing direction for any metal layer is usually perpendicular to the directions for layers above and below it. Other than this guideline, layout is performed without a strict prior arrangement of wires. This can easily give rise to situations where two or more wires are routed together for long distances on the same metal layer, resulting in crosstalk problems.
Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Chapter 4. Fabric1 — Fabric Cell Based Design

Abstract
In the Fabric 1 design methodology, library cells correspond to the standard cells of a standard-cell based design methodology. We call our library cells fabric cells. The routing area between instances of the fabric cells utilizes the DWF fabric. The layout of a fabric cell utilizes the DWF fabric internally. As a result, the DWF fabric is utilized all over the IC layout.
Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Chapter 5. Fabric3 — Network of PLA Based Design

Abstract
This chapter introduces a new design methodology to address the cross-talk problem in DSM VLSI design. This new methodology retains the best features of the Fabric 1 scheme of Chapter 4, with an extremely low area penalty.
Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Chapter 6. Wire Removal in a Network of Plas

Abstract
So far, we have demonstrated that a circuit implementation based on a network of approximately equal-sized PLAs yields a fast, compact, and cross-talk resistant design. The use of minimum-sized transistors in the PLA core results in a fast and dense layout, while a structured arrangement of wires guarantees an effective shielding among signals. The speed and area of each PLA in this design style was reported to be about 50% less than the corresponding standard-cell based implementation.
Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Chapter 7. Conclusions and Future Directions

Abstract
In this chapter we summarize our contributions and point out to some future directions in which this research can be expected to grow.
Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Backmatter

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