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Rolling into modern processor technology, developers are increasing the number of transistors exponentially. NoC is a proficient on-chip communication platform for SoC architecture; partitioning a die into segments and stacking them in 3D fashion significantly reduce latency and energy consumption. A new Cube Network-on-Chip (NoC) based architecture is proposed, which takes the advantage of this exponential increase. In this model, the number of processing elements can be increased exponentially, while reducing the space complexity. In this paper, the thermal impact of the proposed cube NoC model is analyzed. Power and thermal aware hybrid routing method is employed in this model, to improve the reliability and performance. The experimental results reveal that the hybrid routing approach, offers better throughput and failsafe packet delivery, compared to other approaches in the literature.
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Hamedani. P.K, Hessabi. S, Sarbazi-Azad. H, Jerger. N.E., “Exploration of Temperature Constraints for Thermal Aware Mapping of 3D Networks on Chip”, ACM International Journal of Adaptive, Resilient and Autonomic Systems, Volume 4, Issue 3, pp. 42–60, July 2013.
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Jieyi Long, Seda Ogrenci Memik, Gokhan Memik, Rajarshi Mukherjee, “Thermal Monitoring Mechanisms for Chip multiprocessors“, ACM Transactions on Architecture and Code Optimization, Volume 5, Issue 2, Article No. 9, August 2009.
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Shu-Yen Lin, Tzu-Chu Yin, Hao-Yu Wang, An-Yeu Wu, “DTBR: A dynamic thermal-balance routing algorithm for Network-on-Chip”, IEEE Computers & Electrical Engineering, Volume 38, Issue 2, pp. 270–281, March 2012.
- Cube NoC Based on Hybrid Topology: A Thermal Aware Routing
- Springer Singapore
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