From the standpoint of VLSI implementation, the ideal architecture for digital signal processing devices is one which exhibits a high degree of modularity, along with a low degree of interconnectivity between modules. Such a structure not only permits concurrent localized processing, but also avoids the ‘bottleneck’ problem of time-sharing and communicating data to and from a single, high-speed arithmetic ’ processor. Of course, this “parallel processing” approach can be applied to conventional digital signal processing, where typically 8- to 12-bit words are used to represent signal and filtering parameters, but the circuit complexity of multipliers is a deterrent to implementing a large-order system in this manner. Another major problem is simply the amount of chip area that must be devoted to the 8- to 12-bit data buses. These Problems are alleviated i n direct proportion to the amount of reduction in word length that can be accomplished by alternative methods of encoding the signal and system parameters.
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- Data Communication Applications of Incremental Signal Processing
L. E. Franks
F. S. Hill Jr.
- Springer Netherlands
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