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Über dieses Buch

This book describes the design of a receiver front-end circuit for operation in the 60GHz range in 90nm CMOS. Physical layout of the test circuit and post-layout simulations for the implementation of a test chip including the QVCO and the first stage divider are also presented. The content of this book is particularly of interest to those working on mm-wave frequency generation and signal reception.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

The 60 GHz band is an attractive candidate for high data-rate applications, where up to 9 GHz of unlicensed band is available. The IEEE802.15.3c and ECMA-387 standards in the US and Europe regulate this frequency band for high data-rate short-range communication. The high signal loss at 60 GHz suggests using multiple antenna paths for high output power, directive communication. Phase shifts can also be utilized to steer the beem in different directions. This chapter gives an idea about the motivation and target application of this work.

Khaled Khalaf, Vojkan Vidojkovic, Piet Wambacq, John R. Long

Chapter 2. Background

This chapter is going to present the theoretical background needed for the rest of the book. The blocks used in the design are going to be considered. This includes the quadrature voltage-controlled oscillator (QVCO), local oscillator (LO) buffer, injection-locked and static frequency dividers, low-noise amplifier (LNA) and the mixer.

Khaled Khalaf, Vojkan Vidojkovic, Piet Wambacq, John R. Long

Chapter 3. Design and Simulation Results

Schematic simulations at 60 GHz allow the designer to become familiar with a circuit and understand its behavior and changes with different parameters. In this chapter, an evaluation of the active and passive elements used in the technology is first shown. Schematic simulation results for all of the circuit blocks are then presented. This includes the QVCO, LO buffer, divider chain, LNA and mixer blocks.

Khaled Khalaf, Vojkan Vidojkovic, Piet Wambacq, John R. Long

Chapter 4. Top-Level Design

After all the front-end circuit blocks are discussed, the top-level schematic design is going to be presented in this chapter. The circuit performance after putting blocks together is expected to differ from the performance of the blocks separately. This is due to the effect of actual loading of one block by another, as compared to the expected loading while dealing with each section alone.

Khaled Khalaf, Vojkan Vidojkovic, Piet Wambacq, John R. Long

Chapter 5. Layout and Post-layout Simulations

The layout of the QVCO buffer sub-system of Sect. 4.2 is discussed in this chapter. Post-layout simulation results are also provided.

Khaled Khalaf, Vojkan Vidojkovic, Piet Wambacq, John R. Long

Chapter 6. Conclusions

In this work, a receiver front-end at 60 GHz is explored. The circuit includes a QVCO, divider chain, LNA, mixer and LO buffers. A test-chip including the QVCO, LO buffer and the first stage divider is designed to verify the key components of the receiver design. The summary and recommendations for future work are discussed in this chapter.

Khaled Khalaf, Vojkan Vidojkovic, Piet Wambacq, John R. Long

Backmatter

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