Denoising of ECG Signal Using Optimized IIR Filter Architecture—A CSD-Based Design

Signal Processing is a primary and important task in most of the applications involving signal acquisition and digital processing. Signal conditioning can be thought of as a process of removing unwanted information and preserving the required feature of the signal. Denoising can be similarly correlated with signal conditioning in this regard. The presented work is gives an IIR filter architecture that is optimized for area and speed metric for an end application of ECG signal processing. The proposed IIR filter uses Canonic Signed Digits (CSD) for representing scaled version of filter coefficients and then the IIR filter is designed. It is observed that by using CSD-based IIR filter architecture gives an efficient approach to denoise the ECG signals, demonstrates the area reduction by 90%, and improves the speed of operation by 60% when compared with conventional design. The Matlab and Xilinx Vivado platform is used to validate the designed IIR filter and further the post-synthesis implementation details are obtained for Xilinx Virtex-7 series XC7VX485T-2FFG1761C FPGA, Verilog HDL coding is employed to develop the design and stimulus environment for the work.