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Journal of Computational Electronics
Erschienen in: Journal of Computational Electronics 1/2018

22.09.2017

Design and analysis of a gate-all-around CNTFET-based SRAM cell

verfasst von: G. Saiphani Kumar, Amandeep Singh, Balwinder Raj

Erschienen in: Journal of Computational Electronics | Ausgabe 1/2018

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Abstract

This paper proposes a highly stable and low power 6-T static random access memory (SRAM) cell design using a gate-all-around carbon nanotube field effect transistor (GAA-CNTFET). The 6-T SRAM cell is designed and analyzed in HSPICE for different performance metrics viz. SNM, read SNM, write SNM, delay, and leakage power for both the top gate CNTFET and the GAA-CNTFET. The effect of variation of the power supply voltage on the leakage current is also presented, and it was found that the GAA-CNTFET accounts for low power dissipation at higher supply voltage. The 6-T SRAM cell is analyzed for different flat band conditions of the p-type CNTFET taking flatband of the n-type as constant, which is called a dual flat band voltage technique. Through simulations, it is found that by increasing the flatband voltage of a p-type CNTFET, the SRAM gives better performance. The dual flatband variation technique is compared with dual chirality technique, and it is observed that both techniques give the same results.
Vorheriger Artikel Graded channel doping junctionless MOSFET: a potential high performance and low power leakage device for nanoelectronic applications
Nächster Artikel Circuit modeling of the electro-thermal behavior of nanoscale bulk-FinFETs

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Metadaten
Titel
Design and analysis of a gate-all-around CNTFET-based SRAM cell
verfasst von
G. Saiphani Kumar
Amandeep Singh
Balwinder Raj
Publikationsdatum
22.09.2017
Verlag
Springer US
Erschienen in
Journal of Computational Electronics / Ausgabe 1/2018
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-017-1056-x

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