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2021 | OriginalPaper | Buchkapitel

Design and Analysis of a Secure Coded Communication System Using Chaotic Encryption and Turbo Product Code Decoder

verfasst von : S. Khavya, Karthi Balasubramanian, B. Yamuna, Deepak Mishra

Erschienen in: Advances in Computing and Network Communications

Verlag: Springer Singapore

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Abstract

Errors in a transmitted message is unavoidable since noise is inevitable in any communication channel. For reliable transmission of messages, the bit error rate has to be kept at an acceptable rate by the use of proper error control coding schemes. To ensure that the transmission is also secure, data encryption is used as an integral part of the system. This paper deals with the design and analysis of a secure and reliable communication system accomplished using logistic map-based chaotic encryption and turbo product codes. The system is simulated using MATLAB and it is shown that the use of encryption for secure communication does not degrade the system performance. The hardware design of the decoder is also done and verified in Verilog using the same set of vectors as obtained from the system simulation. BER performance was analyzed in all the different scenarios and the correctness of the design was established.
Literatur
1.
Zurück zum Zitat N. Nagaraj, One-time pad as a nonlinear dynamical system. Commun. Nonlinear Sci. Numer. Simul. 17(11), 4029–4036 (2012) MathSciNetCrossRef N. Nagaraj, One-time pad as a nonlinear dynamical system. Commun. Nonlinear Sci. Numer. Simul. 17(11), 4029–4036 (2012) MathSciNetCrossRef
2.
Zurück zum Zitat X. Wu, H. Hu, B. Zhang, Analyzing and improving a chaotic encryption method. Chaos Solitons Fractals 22(2), 367–373 (2004) CrossRef X. Wu, H. Hu, B. Zhang, Analyzing and improving a chaotic encryption method. Chaos Solitons Fractals 22(2), 367–373 (2004) CrossRef
3.
Zurück zum Zitat T. Yang, A survey of chaotic secure communication systems. Int. J. Comput. Cogn. 2(2), 81–130 (2004) T. Yang, A survey of chaotic secure communication systems. Int. J. Comput. Cogn. 2(2), 81–130 (2004)
4.
Zurück zum Zitat R. Bose, A. Banerjee, Implementing symmetric cryptography using chaos functions, in Proceedings of the 7th International Conference on Advanced Computing and Communications (Citeseer, 1999), pp. 318–321 R. Bose, A. Banerjee, Implementing symmetric cryptography using chaos functions, in Proceedings of the 7th International Conference on Advanced Computing and Communications (Citeseer, 1999), pp. 318–321
5.
Zurück zum Zitat R.M. Pyndiah, Near-optimum decoding of product codes: block turbo codes. IEEE Trans. Commun. 46(8), 1003–1010 (1998) CrossRef R.M. Pyndiah, Near-optimum decoding of product codes: block turbo codes. IEEE Trans. Commun. 46(8), 1003–1010 (1998) CrossRef
6.
Zurück zum Zitat K. Eluri, B. Yamuna, K. Balasubramanian, D. Mishra, Low power and area efficient max-log-map decoder, in 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI) (IEEE, 2018), pp. 431–435 K. Eluri, B. Yamuna, K. Balasubramanian, D. Mishra, Low power and area efficient max-log-map decoder, in 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI) (IEEE, 2018), pp. 431–435
7.
Zurück zum Zitat S.N. Vaniya, N. Kumar, C. Sacchi, Performance of iterative turbo coding with nonlinearly distorted ofdm signal, in IEEE Annual India Conference (INDICON) (IEEE, 2016) S.N. Vaniya, N. Kumar, C. Sacchi, Performance of iterative turbo coding with nonlinearly distorted ofdm signal, in IEEE Annual India Conference (INDICON) (IEEE, 2016)
8.
Zurück zum Zitat W. Kuang, R. Zhao, Z. Juan, FPGA implementation of a modified turbo product code decoder, in 2017 IEEE 9th International Conference on Communication Software and Networks (ICCSN) (IEEE, 2017), pp. 71–74 W. Kuang, R. Zhao, Z. Juan, FPGA implementation of a modified turbo product code decoder, in 2017 IEEE 9th International Conference on Communication Software and Networks (ICCSN) (IEEE, 2017), pp. 71–74
9.
Zurück zum Zitat B. Ahn, S. Yoon, J. Heo, Low complexity syndrome-based decoding algorithm applied to block turbo codes. IEEE Access 6, 26 693–26 706 (2018) B. Ahn, S. Yoon, J. Heo, Low complexity syndrome-based decoding algorithm applied to block turbo codes. IEEE Access 6, 26 693–26 706 (2018)
10.
Zurück zum Zitat Y. Krainyk, V. Perov, M. Musiyenko, Y. Davydenko, Hardware-oriented turbo-product codes decoder architecture, in 2017 9th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS), vol. 1 (IEEE, 2017), pp. 151–154 Y. Krainyk, V. Perov, M. Musiyenko, Y. Davydenko, Hardware-oriented turbo-product codes decoder architecture, in 2017 9th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS), vol. 1 (IEEE, 2017), pp. 151–154
11.
Zurück zum Zitat C. Jego, P. Adde, C. Leroux, Full-parallel architecture for turbo decoding of product codes. Electron. Lett. 42(18), 1052–1054 (2006) CrossRef C. Jego, P. Adde, C. Leroux, Full-parallel architecture for turbo decoding of product codes. Electron. Lett. 42(18), 1052–1054 (2006) CrossRef
12.
Zurück zum Zitat M. El Haroussi, I. Chana, M. Belkasmi, VHDL design and FPGA implementation of a fully parallel BCH SISO decoder, in 2010 5th International Symposium on I/V Communications and Mobile Network (IEEE, 2010), pp. 1–4 M. El Haroussi, I. Chana, M. Belkasmi, VHDL design and FPGA implementation of a fully parallel BCH SISO decoder, in 2010 5th International Symposium on I/V Communications and Mobile Network (IEEE, 2010), pp. 1–4
13.
Zurück zum Zitat C. Leroux, C. Jégo, P. Adde, M. Jézéquel, High-throughput block turbo decoding: from full-parallel architecture to FPGA prototyping. J. Signal Process. Syst. 57(3), 349–361 (2009) CrossRef C. Leroux, C. Jégo, P. Adde, M. Jézéquel, High-throughput block turbo decoding: from full-parallel architecture to FPGA prototyping. J. Signal Process. Syst. 57(3), 349–361 (2009) CrossRef
14.
Zurück zum Zitat T.S. Chaware, B. Mishra, Secure communication using TPC and chaotic encryption, in 2015 International Conference on Information Processing (ICIP) (IEEE, 2015), pp. 615–620 T.S. Chaware, B. Mishra, Secure communication using TPC and chaotic encryption, in 2015 International Conference on Information Processing (ICIP) (IEEE, 2015), pp. 615–620
15.
Zurück zum Zitat L. Kocarev, Chaos-based cryptography: a brief overview. IEEE Circ. Syst. Mag. 1(3), 6–21 (2001) CrossRef L. Kocarev, Chaos-based cryptography: a brief overview. IEEE Circ. Syst. Mag. 1(3), 6–21 (2001) CrossRef
16.
Zurück zum Zitat K.T. Alligood, T.D. Sauer, J.A. Yorke, Chaos (Springer, Berlin, 1996) K.T. Alligood, T.D. Sauer, J.A. Yorke, Chaos (Springer, Berlin, 1996)
17.
Zurück zum Zitat M. Ausloos, M. Dirickx, The logistic map and the route to chaos: From the beginnings to modern applications (Springer Science & Business Media, Berlin, 2006) M. Ausloos, M. Dirickx, The logistic map and the route to chaos: From the beginnings to modern applications (Springer Science & Business Media, Berlin, 2006)
18.
Zurück zum Zitat P. Mathew, L. Augustine, T. Devis, et al., Hardware implementation of (63, 51) bch encoder and decoder for WBAN using IFSR and BMA P. Mathew, L. Augustine, T. Devis, et al., Hardware implementation of (63, 51) bch encoder and decoder for WBAN using IFSR and BMA
19.
Zurück zum Zitat A. Ambat, K. Balasubramanian, B. Yamuna, D. Mishra, FPGA implementation of an efficient high speed max-log-map decoder, in 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI) (IEEE, 2018), pp. 747–751 A. Ambat, K. Balasubramanian, B. Yamuna, D. Mishra, FPGA implementation of an efficient high speed max-log-map decoder, in 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI) (IEEE, 2018), pp. 747–751
Metadaten
Titel
Design and Analysis of a Secure Coded Communication System Using Chaotic Encryption and Turbo Product Code Decoder
verfasst von
S. Khavya
Karthi Balasubramanian
B. Yamuna
Deepak Mishra
Copyright-Jahr
2021
Verlag
Springer Singapore
DOI
https://doi.org/10.1007/978-981-33-6977-1_48