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Erschienen in: Real-Time Systems 2/2020

15.11.2019

Design and analysis of SIC: a provably timing-predictable pipelined processor core

verfasst von: Sebastian Hahn, Jan Reineke

Erschienen in: Real-Time Systems | Ausgabe 2/2020

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Abstract

We introduce the strictly in-order core (SIC), a timing-predictable pipelined processor core. SIC is provably timing compositional and free of timing anomalies. This enables precise and efficient worst-case execution time (WCET) and multi-core timing analysis. SIC’s key underlying property is the monotonicity of its transition relation w.r.t. a natural partial order on its microarchitectural states. This monotonicity is achieved by carefully eliminating some of the dependencies between consecutive instructions from a standard in-order pipeline design. We present a formal proof framework based on satisfiability modulo theories that is able to automatically verify SIC’s timing predictability. SIC preserves most of the benefits of pipelining: it is only about 6–7% slower than a conventional non-strict in-order pipelined processor. Its timing predictability enables orders-of-magnitude faster WCET and multi-core timing analysis than conventional designs.

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Metadaten
Titel
Design and analysis of SIC: a provably timing-predictable pipelined processor core
verfasst von
Sebastian Hahn
Jan Reineke
Publikationsdatum
15.11.2019
Verlag
Springer US
Erschienen in
Real-Time Systems / Ausgabe 2/2020
Print ISSN: 0922-6443
Elektronische ISSN: 1573-1383
DOI
https://doi.org/10.1007/s11241-019-09341-z