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This paper presents the design and the experimental characterization of an 800 V 11 kVA three-level three-phase active neutral point clamped inverter, utilizing 650 V gallium nitride enhancement-mode high-electron-mobility transistors. The proposed scaled-down prototype design has been developed for electric traction systems. The modular approach of the presented power converter design is discussed in detail, and the different parts composing the power conversion unit are presented. Moreover, critical issues related to the design of power converters employing gallium nitride technology are highlighted for both power and gate driving sections. In addition, PCB’s thermal analysis and parasitic extraction are discussed, and for the latter the results of the conducted finite element analysis are reported. Experimental characterization of the designed prototype is performed on a 7.5 kW induction motor drive. Experimental results are reported, and the power conversion unit’s performances are evaluated in terms of efficiency at different operating conditions of the electric drive.
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1 Introduction
Nowadays, the inadequate range of electric powertrains is one of the main reasons hindering the widespread adoption of electric vehicles (EVs). Long battery charging times compared to the equivalent category of internal combustion vehicles is a further limitation together with poor battery autonomy generally less than 450 km as an optimistic estimation. Reduction in charging times could be a good compensation for the autonomy issue from the consumer's point of view. A higher charging power can reduce the battery refueling time, and for this reason EV manufacturers are currently working on 800 V-battery pack solutions, since an increase in dc current range would bring higher losses [1‐4].
At the same time, traction electric drives are required to feature high efficiency, compactness, high power density, high reliability and low weight [5, 6]. Power electronics is playing an increasingly important role in electric vehicles. The process of vehicle electrification requires an integrated approach that focuses on innovation in semiconductor technologies and power converter topologies. Concerning semiconductor technologies, wide-bandgap (WBG) devices based on materials such as gallium nitride (GaN) and silicon carbide (SiC) are spreading more and more in the field of power electronics. These technologies provide some advantages with respect to conventional silicon (Si) devices, such as higher electric breakdown field, higher energy gap, higher electron saturation velocity, higher electron mobility and higher thermal conductivity. Higher electric breakdown field and electron mobility guarantee lower on-resistance which allows obtaining smaller sizes of WBG devices with equal current ratings. Moreover, higher electron saturation velocity brings the possibility of working with higher switching frequencies. SiC devices constitute a robust solution for high-power, high-voltage and high-temperature applications, while GaN power devices are more suitable for high-efficiency and high-frequency applications, due to extremely low on-resistances and very high saturated electron velocity [7].
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The integration of GaN devices’ capability to operate at elevated switching frequencies, combined with compact output passive filtering, makes them a promising solution to be employed in voltage source inverters (VSI) for electric traction. In fact, this feature improves the electromagnetic and thermal behavior of the motor downstream, reducing the power converter’s output filter parameters and thus reducing the total size of the power conversion system [8, 9]. In the market, the most widespread GaN high-electron mobility transistors (HEMTs) feature a rated drain-to-source breakdown voltage equal to 650 V. This feature limits their employment in traditional two-level power conversion units for electric traction with high dc-bus voltages [10]. For this reason, GaN-based multilevel inverter topologies are considered an effective technical solution for the next generation of electric traction units operating at high dc voltages. Indeed, in multilevel inverters the dc-bus voltage is shared among different devices, reducing the power switches’ drain-to-source voltage stress, thus overcoming the breakdown voltage limitation of GaN technology. In addition, despite higher cost and complexity, multilevel topologies can be considered to gain some benefits in the overall electric drive. They feature a reduced dv/dt stress on the electric load, a reduction of common-mode voltages and a further reduction of the total harmonic distortion (THD) of the output quantities, and they allow reaching higher efficiency and reducing the complexity and size of input/output filters [11‐13].
Active neutral point clamped (ANPC) is a promising multilevel inverter’s topology since it allows better distribution of losses and stress among power switches; thus, it potentially enables a substantial performance improvement for high-power electrical drives [14‐16]. Hence, ANPC topology has been conceived in this study to overcome this limit.
In the literature several designs for a three-level GaN-based ANPC converter have been presented, as, for instance, in [17‐20]. In [17] and [18] GaN power modules are proposed for a half-bridge three-level ANPC inverter, where power, driving and conditioning circuits are integrated on the same printed circuit board (PCB). In [17], an eight-layer printed circuit board (PCB) is used, and GaN HEMTs are parallel operated according to the chosen modulation strategy, with three devices operating at high switching frequency and two devices switching at low frequency. In [18], a four-layer PCB is employed, with GaN HEMTs placed on the top and bottom layers, and their switching pattern is controlled via optical receivers. In [19], a half-bridge three-level ANPC inverter is presented with an insulated metal core substrate (IMS) power section for bottom-side cooled GaN HEMTs, accompanied by two other PCBs for driving and power supply with a vertical totem stack configuration. The designed prototype is demonstrated at 5.1 kW for a 70 kHz switching frequency at 550 VDC. In [20], a three-phase three-level ANPC inverter is proposed, where power, driving and conditioning circuits are placed on a two-layer PCB. GaN HEMTs’ switching is controlled via an STM32 microcontroller which can be plugged into the board.
Starting from the investigation of the state-of-the-art GaN-based ANPC inverters, the design of a new three-phase, three-level modular ANPC inverter was developed and previously presented in [21]. The proposed design methodology incorporates an integrated approach, including preliminary analyses such as monitoring potential PCB hot spots and parasitic extraction, the latter being performed using the Ansys Q3D Extractor tool. During the design phase, particular emphasis has been placed on the modularity of the power conversion unit, in terms of control approach, employed power devices and even the converter topology. In order to achieve such high flexibility, power, driving and control sections have been sundered. Therefore, changes can be made by simply acting on small boards, saving time and costs. The designed power conversion unit consists of the following modules:
A main board housing power supply, dc-side and ac-side voltage and current sensing;
Three single-phase power cells consisting of six GaN HEMTs, decoupling capacitors and RC snubbers, the last to mitigate drain-to-source overvoltages;
Three driving boards with isolated gate drivers and a dual output dc/dc stage for each device, with the aim to eliminate the need for any additional conditioning circuit;
Two control boards enabling the alternative control of switching devices with either optical fibers or STM32.
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Moreover, the modular structure allows integrating an output low-pass filter integrated on the inverter’s main board. High switching frequencies can negatively affect the electrical machine's lifetime by contributing to insulation deterioration, leading to motor failure. However, high switching frequencies also enable the design of very compact output filters. Therefore, it becomes feasible to implement a passive filter directly into the GaN inverter, eliminating the need for a bulky and costly filter inductor [22, 23].
The remaining part of the paper is organized as follows. Section 2 analyzes the topology and the modulation strategies that were considered in the implementation of the ANPC inverter. In Sect. 3 the converter’s layout is presented, describing all the boards composing the power conversion unit. In Sect. 4, an estimation of power loop parasitic inductances for the GaN board is presented, conducted through a finite-element analysis (FEA) using Ansys Q3D Extractor software. Section 5 reports the monitoring of eventual hot spots in the PCB, by evaluating the predicted dc current density distribution through the Altium PDN Analyzer tool. Section 6 reports the experimental tests carried out on the designed prototype in a regenerative motor drive, evaluating the performances of the power converter in terms of efficiency. Finally, Sect. 7 provides concluding remarks.
2 ANPC inverter topology
In three-phase and three-level ANPC topology (Fig. 1), each leg is made up of six power devices. Among them, two power switches per leg, Sk5 and Sk6 (where k = A, B, C), are in charge of clamping the phase output voltage to the neutral point of the dc-bus when a 0 V state is required in the ac side. The name comes from these two ‘active’ devices, unlike the NPC in which two diodes are used as clamping devices. The switching states are reported in Table 1 where k = A, B, C and VAO is the single-phase power cell’s output voltage. By acting on the modulation technique, different switching patterns can be obtained allowing for differently shared conduction and switching losses among power devices.
In the literature, numerous multicarrier strategies have been developed for multilevel inverters with the aim of reducing the high-frequency harmonic content of the output voltage, increasing the linear region, improving the fault-tolerance capability. Some methods use carrier disposition, as in the phase-disposition (PD) strategy, while others use phase shifting of multiple carrier signals [24]. Some modulation strategies have been specifically proposed for ANPC, such as the diode neutral point clamped modulation (DNPC), the ANPC modulation with same-side clamping (ANPC-SSCM), the ANPC modulation with opposite-side clamping (ANPC-OSCM) and the ANPC with full-path clamping (ANPC-FPCM). The latter implies PWM switching for all the devices for half of the fundamental period, allowing to have better current sharing among the power devices, reducing the overall losses of the ANPC converter [16]. On the contrary, according to [25], ANPC-OSCM has been demonstrated to be very effective in terms of common-mode noise reduction.
In the presented solution, all the aforementioned sinusoidal pulse-width modulation (SPWM) techniques can be implemented in addition to space vector pulse-width modulation (SVPWM). The latter produces lower harmonic distortion than SPWM and allows for better utilization of the dc-bus.
3 ANPC inverter prototype design
The designed power conversion unit consists of a main board where power (Sect. 3.1), driving (Sect. 3.2) and control (Sect. 3.3) boards are externally plugged into. The main board is a four-layer PCB that comprises power connectors, dc-link, dc and ac current and voltage sensing circuits, and the sockets devoted to external sections’ connections. The main board’s dc-side is made up of input connectors for supplying both power and signal sections. In addition, the sensing circuits are responsible for sensing the dc and ac voltages and currents, enabling not only the measurement of these electrical quantities but also providing feedback analog signals to the control board. This allows the implementation of control strategies without the need for any external circuitry, a crucial aspect in reducing the overall size of the electric drive.
The dc-link capacitors are in charge of keeping the dc input voltage stable. Specifically, four electrolytic capacitors have been chosen due to their highest capacitance-to-volume ratio, making them ideal for the reduction of dc-bus voltage ripple. The capacitance value CDC is chosen according to (1), [26], with the aim of keeping the oscillations within the limits of ± 5%. In (1), Vpp is the peak-to-peak dc voltage, fsw is the rated switching frequency (100 kHz), and Imax is the maximum value of the output current.
Nevertheless, electrolytics have considerably high equivalent series resistance (ESR) and equivalent series inductance (ESL). The minimization of parasitic components together with the optimization of the layout is crucial to deal with. Indeed, high signal edge rates imply that the performance of the power conversion unit is heavily affected by parasitic components [27]. Parasitic resistances, capacitances and inductances can create oscillations and EMI and can cause failures. Parasitic resistances are inversely proportional to the area of the trace; thus, it could be enough to increase the section of the trace. When some limitations occur in enlarging the trace for layout optimization purposes, it is possible to mitigate stray resistances by simply increasing the PCB copper layer’s thickness. Parasitic capacitances can constitute a potential cause of capacitive noise coupling when high dv/dt occurs. Since self or mutual capacitive effects can occur, there are different ways to mitigate parasitic capacitances. In the case of self-capacitive effects, it is enough to increase the distance between conductors. In the case of mutual capacitive effects, it is generally preferred to increase self-capacitance by routing the ground plane of that conductor in a closer layer. Parasitic inductances are also very crucial to deal with, due to their evaluation complexity, since they depend on the PCB traces’ routing and the current path and flowing direction. Moreover, mutual inductive contributions can increment or reduce the overall parasitic inductive loop.
In the designed ANPC prototype, minimization of parasitic inductive loops has been pursued both for the power commutation loop and for the gate driver loop. The former consists of parasitic inductive contributions which involve dc-link and switching cell traces; the latter involves the driving circuit path from the gate driver to the gate pin of the respective GaN HEMT. In the main board, six low ESR and ESL multi-layer ceramic capacitors (MLCCs) are paralleled to the bulk capacitors to counteract the undesired effects of ESR and ESL, thus reducing the parasitic power loop. They are positioned as close as possible to the connectors of the GaN boards to minimize the impact of stray inductances on transient commutations which are significant at high switching frequencies [28].
The minimization of parasitic power and gate loops has been stressed in the design of GaN and driving board, respectively. As can be noticed in Fig. 2, they are orthogonally mounted on the main board and reciprocally connected by means of transversal male-to-female connectors which are in charge of providing gate-to-kelvin source voltages to respective pins of GaN HEMTs.
The sundering of power and driving sections in such “sandwich” architecture (Fig. 3) has implied some additional issues during the design stage. Indeed, the distance between GaN and driving boards must comply with the minimization of parasitic gate loop and with the need to ensure that there is enough space for measurement probes inside the sandwich structure. Due to this trade-off, transversal connectors must feature low intrinsic parasitic inductance and adequate height. Despite this additional complexity, the sundering of power and driving sections allows mitigating the crosstalk phenomenon which usually has a detrimental effect especially on low-voltage signals in terms of signal integrity. In addition, this design choice simplifies the layout of the two boards whose routings are not affected by EMI criteria leading to layout optimization and reduction of the power conversion unit’s size.
Fig. 3
Modular architecture for power and driving stages’ connection
GaN board is shown in Fig. 4. It consists of a single- phase ANPC switching power cell. It comprises a decoupling capacitive stage for each half of the dc-bus, and six SGT65R65AL e-mode GaN HEMTs (Table 2) manufactured by STMicroelectronics.
Drain-to-source blocking voltage (transient < 1 µs)
750V
Gate-to-kelvin source voltage
− 10V–7V
Drain current (continuous)
25 A
Typical static drain–source on-resistance
49 mΩ
Maximum static–source on-resistance
65 mΩ
Operating junction temperature
− 55C–+ 150C
Turn-on switching energy
33.8 µJ
Turn-off switching energy
19.5 µJ
Since the employed GaN HEMTs are bottom-side cooled devices, the GaN board has been realized using IMS technology to maximize the heat dissipation of the bottom-side cooled devices. Indeed, IMS offers lower case-to-heat sink thermal resistance compared to a standard stackup made of copper layers with interleaved FR-4 core. However, the IMS solution limits the layout design to a single-layer PCB, preventing the use of through-hole components and vias, which are often useful for minimizing conductive paths.
To minimize the parasitic power loop’s overall inductance, a further decoupling capacitor stage has been placed in the GaN board in addition to the main board’s one. It consists of C1812C204KDRLCAUTO multilayer ceramic capacitors which feature extremely low ESL. Moreover, the presence of the heat sink on the bottom face of the board makes possible the placement of the decoupling capacitor stage in the proximity of the switching section, minimizing ringing on GaN HEMTs’ commutations [29].
It is well known the feasibility to feature high di/dt in GaN-based technology: typically, until 5 A/ns in case of soft switching, 15 A/ns in case of hard switching. For this reason, even small stray inductive contributions could be responsible for generating a voltage drop which could cause relevant drain-to-source overvoltages, especially in turn-off switching transients of GaN HEMTs. Therefore, together with the pursuing of minimized power loop parasitic inductance, some additional RC snubbers can be expected and can be connected in parallel to each power device to smooth transient overvoltages. Although this results in an extra dissipation of energy and slower commutations, the increase in dissipated energy is very modest, considering the low intrinsic output capacitance of GaN HEMTs. The benefit of reduced overvoltages brings a substantial advantage in placing snubbers [30].
3.2 Driving board
The four-layer driving daughterboard, as shown in Fig. 5, consists of a dc/dc stage and a driving circuit for each GaN HEMT of the ANPC leg.
The dc/dc stage consists of MGN1D050603MC-R7 dual output 1W isolated dc-dc converters, which convert the 5 V input voltage (properly smoothed by means of a by-pass capacitor) to 6V/-3V output voltage levels. The optimal on-state gate voltage for SGT65R65AL is 6V, whereas the negative bias (-3V) for the turning-off voltage increases immunity to spurious gate bouncing and false switch turn-on (shoot-throughs). The use of a dual dc-dc converter allows significantly reducing the size of the dc-dc stage since no additional conditioning circuit is required. Dc-dc converter's output voltage levels are exploited as output reference voltages of the STGAP2GSNCTR, the galvanically isolated gate driver used to drive the GaN HEMTs. The gate driver is the core element of the driving circuit, whose schematic is illustrated in Fig. 6. Gate resistances Rg(on) and Rg(off) are important to set how fast the device goes through the turning-on and the turning-off, respectively. Their values are determined according to the inequalities in (3) and (4), where VH − GNDISO is the voltage difference between the two output voltage values provided to the gate driver’s output pins and thus 9 V. RDS(on) is the typical static drain-source on-resistance, while IOH and IOL are the maximum allowed output currents during the turning-on and the turning-off transients, which for the employed gate driver are equal to 2.5 A and 3.75 A, respectively.
Rg(on) is set to 10 Ω, whereas Rg(off) is set to 2.2 Ω. In addition, a large pull-down resistor R1 is added to divert the current that can potentially charge the parasitic gate-to-source capacitance, avoiding the Miller turn-on phenomenon.
The proposed board’s layout considers the optimization of the gate driver loop since it is one of the most crucial design aspects to deal with when high dv/dt and di/dt occur [31]. Because of the common source inductance/mutual inductance, the di/dt of the power loop can easily affect the gate-to-kelvin source voltage during the switching [32]. In particular, stray inductive components can lead to oscillations, potentially resulting in shoot-through events due to undesired turn-on of the device, with the risk of failure of the entire power cell. To minimize parasitic inductance in the gate loop, the physical distance between the gate driver and the device’s gate pin has been minimized. Furthermore, to reduce signal trace lengths, the use of small-width components (0603 package) has been essential, allowing for extremely short conductive paths without the need for vias. This design choice significantly reduces parasitic gate loop inductance, ensuring signal integrity and enabling high-speed operation. As previously mentioned, the separation of the driving and power sections has also contributed to improved signal integrity and layout optimization.
Finally, one of the PCB’s inner layers has been exploited to extend the ground plane of gate drivers’ input signals to guarantee a return current path in an adjacent layer with respect to the one in which they are routed. This creates a vertical flux cancelation that further reduces the gate loop stray inductance.
3.3 Control interface board
The control interface board is responsible for providing PWM signals to the gate drivers. As evidence of the emphasized modular approach, two alternative four-layer versions of this board have been designed: one featuring optical receivers and the other based on an STM32 microcontroller.
Optic control interface board, as shown in Fig. 7, consists of 18 (one for each device) optical receivers (660 nm wavelength, 1 Mbd data rate) and their respective by-pass capacitors. This board allows control of the converters’ switches with field-programmable gate array, dSpace or microcontroller.
STM32-adapter board, as shown in Fig. 8, consists of two connectors to plug in the analog-32pins and the digital-68pins of a control board for STM32-G474QET6 Mainstream ARM Cortex-M4 microcontroller.
As already explained in Sect. 3, minimization of parasitic components leads to smoothing overshoots in drain-to-source voltages and reducing GaN HEMTs’ switching losses. Parasitic estimation is necessary to check the layout’s symmetry which is crucial to guarantee a better share of electrical stress and losses among power devices.
Parasitic resistance is easy to estimate, since it strongly depends on the dimensions of the trace. Though parasitic capacitance Cσ cannot be eliminated, it can be easily evaluated as in (4), where εr is the PCB dielectric’s relative permittivity, while ε0 is the vacuum permittivity, A is the overlapping area of involved planes and d is the distance between the two conductors [33].
Each parasitic self-inductive component Lσ can be roughly evaluated as in (5), where µr is the FR-4 relative permeability, µ0 is the air permeability, h is the copper layer thickness, and l and w are the length and the width of the considered trace, respectively.
However, the determination of the overall inductive contributions (including self and mutual inductances) of a trace is not trivial. For this reason, in the presented work, the Ansys Q3D Extractor tool has been exploited. Notably, parasitic inductive contributions of the power loop have been estimated. A finite element analysis (FEA) has been conducted on the GaN board which mainly comprises the power loop. The overall power loop’s parasitic inductance can be split into single contributions relative to the traces that make it up. Figure 9a shows the electrical circuit comprehensive of the single inductive contributions associated with the layout traces illustrated in Fig. 9b. Parasitic inductances’ behavior has been observed in a large frequency spectrum, firstly conducting a dc analysis and then an ac one at 100 kHz (equal to target fsw). Stray inductances’ values obtained at 100 kHz are reported in Table 3.
Fig. 9
Electrical circuit a comprehensive overview of stray inductances related to GaN board’s designed traces b
Parasitic inductances estimated at 100 kHz with Ansys Q3D Extractor
Inductance
Value
Inductance
Value
Lp
14.46 nH
Ln
22.04 nH
L1−2
5.08 nH
L4-3
3.78 nH
L1−5
5.72 nH
L4-6
6.15 nH
L0−5
13.93 nH
L0-6
11.04 nH
L2−3
4.84 nH
Finite element analysis (FEA)’s results evidence low stray inductances in GaN board (average of 10nH) even without considering the presence of decoupling capacitors. Moreover, GaN board’s layout features good symmetry according to the FEA: L1 − 2 is almost equal to L1 − 5, and the same happens for L4 − 3 and L4 − 6 and for LO − 5 and LO − 6. The power traces which come from connectors to main board (Lp, Ln, LO − 5 and LO − 6) have higher values, as expected considering the length of the traces shown in Fig. 9b and from (5).
5 PCB hot spots monitoring
In medium- and high-power applications, thermal analysis is crucial. Indeed, thermal issues must be considered to ensure reliability and the longest system’s lifetime possible. Thermal issues do not involve just power devices’ heat dissipation and thus the design of a proper cooling system. A crucial issue to deal with is related to the potential damage of the PCB due to critical thermal conditions. An inadequate layout and stackup with target current ratings could bring excessive heating regions and the creation of hot spots. Hot spots are PCB regions that get too much heat, and this can result in the lifting of pads and traces, and in PCB delamination and warpage [34, 35].
For this reason, during the design stage a dc analysis has been conducted on the GaN board’s final layout to identify the most critical points of the PCB in terms of heat dissipation. This analysis has been carried out by exploiting the Altium PDN Analyzer tool, and the current density post-processing results are illustrated in Fig. 10. As Altium PDN Analyzer allows only dc analysis, the ANPC power cell’s states in Table 1 have been individually considered.
Fig. 10
Dc current density distribution in ANPC power cell: P state a, 0 + state b, 0- state c and N state d
Simulation results are organized as heat maps for each power cell’s state with arrows to indicate the current flow direction. In each state large traces have a laterally asymmetric current distribution since current follows the shortest path, thus concentrating on the inner side of the rounded power polygons. Moreover, simulation results show hot spots limited to areas where copper is more present, that is, in correspondence with GaN HEMTs pads and power connectors. It has been verified that there are not critical issues related to the layout like bottlenecks of power traces that could damage the PCB and have a detrimental effect on the power cell’s performances.
6 Experimental results
The designed three-phase three-level ANPC inverter prototype has been experimentally tested. An experimental test bench (Fig. 11) has been assembled including a regenerative motor drive configuration to emulate the torque-speed traction characteristics. Sinusoidal PWM with same-side clamping modulation strategy has been implemented in a STMicroelectronics STM32-G474QET6 and provided to the driving section by exploiting the designed STM32-adapter board described in Sect. 3.3. The dc motor of the regenerative motor drive has been controlled by means of a SCALEXIO dSpace. Operating conditions of experimental tests are reported in Table 4.
Gate-to-kelvin source voltages Vgks of GaN HEMTs have been monitored, together with the corresponding drain-to-source voltages Vds, the line-to-line output voltages and the phase output currents ia, ib and ic. Figure 12 reports these waveforms at 600 V of dc-bus, 7.2 kW of output power Pout, 50 kHz of switching frequency fsw and 0.95 of amplitude modulation index ma. Although the gate-to-kelvin source voltage waveform evidences some high-frequency spikes especially during the off-state, it is steadily contained inside the absolute range of the GaN HEMT, i.e., 7 V/-10 V. Moreover, the drain-to-source voltage is steadily close to half of the dc-bus voltage, owing to the minimization of parasitic inductances and the additional paralleling of RC snubbers (10 Ω, 200 pF). At the same time, the benefits of the layout optimization stage are evidenced by the quality of the line-to-line inverter’s output voltage: indeed, the expected five voltage levels (Vdc, + Vdc/2, 0 V, -Vdc/2, Vdc) are clearly visible and the waveform does not evidence significant overvoltage at the inverter’s output connectors. Moreover, phase output currents feature low harmonic distortion and good waveform’s symmetry.
Fig. 12
Gate-to-kelvin source voltage of SC4 (green), drain-to-source voltage (violet) of SC4, inverter’s line-to-line output voltage (red) and phase output currents ia (blue), ib (orange) and ic (yellow) at VDC = 600 V
Line-to-line voltage Vab has been monitored not only at inverter’s output connectors, as shown in Fig. 12, but even at motor terminals. As widely investigated in the literature, the presence of the cable connecting the power converter with downstream motor produces overvoltages at the motor terminals due to impedance mismatches, especially when high dv/dt occurs, [36]. Figure 13 displays this phenomenon.
Fig. 13
Inverter’s output connectors-measured (orange) and motor terminals-measured (blue) line-to-line voltage, and common-mode voltage (red) in three switching periods
Moreover, it also shows the common-mode voltage VCM, evaluated between the neutral point of the dc-bus and the motor star-point. The experimental common-mode voltage varies between ± VDC/3 (-200V in Fig. 13) and ± VDC/6 (-100V in Fig. 13) with slight ripple, depending on the combination of active switching states. This behavior is fully consistent with theoretical expectations for a three-level inverter topology and confirms the significant reduction in common-mode voltage compared to a conventional two-level inverter.
Experimental characterization of the designed three-phase three-level GaN ANPC inverter prototype has been carried out in terms of efficiency η, over a wide range of operating conditions of the drive, defined by mechanical torque Tm and speed n. Figure 14 reports the power converter’s efficiency at different torque and speed levels. Efficiency remains higher than 97% in a wide operating range.
Fig. 14
Three-phase and three-level ANPC inverter’s efficiency and relative output active power at different torque and speed conditions
In addition, the power converter’s efficiency has been evaluated at different modulation indices and switching frequencies, with a dc-bus voltage equal to 600V and with a medium output power equal to 4.36kW. Figure 15 reports that the power converter’s efficiency is greater than 95% even at higher switching frequencies, such as 100 kHz.
Fig. 15
Three-phase and three-level ANPC inverter’s efficiency at different amplitude modulation indices and switching frequencies under medium load
The key findings of the research presented in this work can be summarized as follows:
1.
The iterative design approach used in the proposed approach, focusing on minimizing stray inductances and optimizing current density distribution, successfully achieved a high-quality synthesis of inverter output voltages.
2.
The proposed modular configuration of the converter demonstrated high efficiency in a wide operating range.
3.
Preliminary results highlighted a critical issue with high dv/dt at the motor terminals, which could significantly impact motor reliability. To address this challenge, ongoing work is focused on integrating a tailored output filter to mitigate electrical stress at the motor terminals while maintaining overall system efficiency.
Acknowledgements
This work has been carried out within the ECSEL-JU project GaN4AP (GaN for Advanced Power Applications), under grant agreement no. 101007310. This Joint Undertaking receives support from the European Union’s Horizon 2020 research and innovation programme.
Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article's Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creativecommons.org/licenses/by/4.0/.
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