Design and Test of a Radiation-Hardened 14-Bit 80 MS/s SAR-Assisted Pipeline-ADC in 28-nm Bulk-CMOS

This paper presents the design, implementation, and experimental validation of a 14-bit 80 MS/s calibration-free radiation-hardened pipeline analog-to-digital converter (ADC) realized in 28-nm bulk-CMOS technology. The escalating demand for high-performance ADCs in radiation-rich environments requires robust designs capable of withstanding ionizing radiation-induced errors without compromising performance. Traditional radiation-hardened ADC solutions often entail complex calibration procedures, leading to increased power dissipation and design complexity. In contrast, our proposed ADC architecture leverages the inherent advantages of the pipeline topology, coupled with innovative circuit techniques, to achieve resilience to radiation-induced errors without the need for calibration. By eliminating calibration overhead, the proposed design minimizes energy consumption while maintaining high precision and throughput. The paper outlines the architectural principles, circuit implementations, and the radiation-hardening techniques employed in the ADC design. The performance of the ADC was experimentally characterized for normal operation and for a total-ionizing dose (TID) of 100 krad(Si). The circuit was also tested for single-event effects (SEE), covering single event upset (SEU), single-event latch-up (SEL) and single-event transient (SET) under heavy ions radiation. This calibration-free pipeline ADC represents a significant advancement in radiation-hardened ADC design, offering a compelling solution for applications in space missions, nuclear facilities, and other radiation-prone environments where reliability and energy efficiency are paramount.