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Journal of Computational Electronics

Erschienen in:

14.05.2023

Design considerations for engineering \(\hbox {HfS}_2\) negative capacitance FET through multilayered channel and \(\hbox {Hf}_{1-x}{\hbox {Zr}_{x}}\hbox {O}_2\)/\(\hbox {HfO}_2\) double-gate stacks: an ab initio and NEGF study

verfasst von: Mayuri Sritharan, Hyunjae Lee, Robert K. A. Bennett, Youngki Yoon

Erschienen in: Journal of Computational Electronics | Ausgabe 5/2023

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Abstract

The implementation of highly promising monolayer two-dimensional materials in conventional field-effect transistors (FETs) subjects these materials to the classical switching limit inhibiting their potential for steep-switching FET technology. In this work, we propose a practical double-gate negative capacitance (NC) FET design that leverages the use of multilayer \(\hbox {HfS}_2\) channel in conjunction with a compatible \(\hbox {Hf}_{1-x}{\hbox {Zr}_{x}}\hbox {O}_2\)/\(\hbox {HfO}_2\) ferroelectric–dielectric (FE–DE) stack to boost the performance potential of \(\hbox {HfS}_2\). The layer-dependent material properties are modelled using ab initio density functional theory (DFT) calculations, which are transformed onto the maximally localized Wannier function (MLWF) basis to extract tight-binding-like Hamiltonians for the channel region. Devices are investigated by means of quantum transport simulations considering both single-gate (SG) and double-gate (DG) geometries benchmarked against conventional MOSFETs. In the SG case, the NCFET demonstrates improved SS (through internal voltage amplification) with steep-switching performance in mono- and bilayer cases, with the monolayer case exhibiting > 10\(^{10}\) maximum ON/OFF ratios and nearly a 37 mV/decade improvement in SS compared to the SG-MOSFET. In the DG case, the NCFET demonstrates superior gate control achieving steep-switching performance from one to four layers, which is, however, accompanied with increased hysteresis. We further demonstrate that multilayer channels may actually outperform their monolayer counterparts when simultaneously optimizing subthreshold performance and hysteresis. By balancing the trade-off between SS and hysteresis through layer engineering and capacitance matching, we have demonstrated a trilayer \(\hbox {HfS}_2\) DG-NCFET device with SS \(\sim\) 46 mV/decade and hysteresis \(\sim\) 12 mV.

Vorheriger Artikel Multi-scale simulations of two dimensional material based devices: the NanoTCAD ViDES suite

Nächster Artikel Electronic, transport and ballistic device properties of quasi-one-dimensional GeS

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Titel: Design considerations for engineering negative capacitance FET through multilayered channel and / double-gate stacks: an ab initio and NEGF study
verfasst von: Mayuri Sritharan
Hyunjae Lee
Robert K. A. Bennett
Youngki Yoon
Publikationsdatum: 14.05.2023
Verlag: Springer US
Erschienen in: Journal of Computational Electronics / Ausgabe 5/2023
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI: https://doi.org/10.1007/s10825-023-02036-6

Ab-initio simulation of dissipative transport in tunnel devices based on heterostructures of 2D materials

Modeling of inversion layer capacitance of III-V double gate MOSFETs using a neural network-based regression technique

Analytical modeling and quasi-static characterization of a lithium niobate (LiNbO3)-based metal–ferroelectric–metal–insulator–semiconductor (MFMIS) NCFET

Microwave properties of a double wire array

Multi-scale simulations of two dimensional material based devices: the NanoTCAD ViDES suite

Open Access

Resistance saturation in semi-conducting polyacetylene molecular wires

Open Access

Springer Professional

Abstract

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Ab-initio simulation of dissipative transport in tunnel devices based on heterostructures of 2D materials

Modeling of inversion layer capacitance of III-V double gate MOSFETs using a neural network-based regression technique

Analytical modeling and quasi-static characterization of a lithium niobate (LiNbO3)-based metal–ferroelectric–metal–insulator–semiconductor (MFMIS) NCFET

Microwave properties of a double wire array

Multi-scale simulations of two dimensional material based devices: the NanoTCAD ViDES suite

Resistance saturation in semi-conducting polyacetylene molecular wires