Design for Boundary-Scan Test

Design for Testability (DFT) is a subject covering a huge amount material. The 1983 survey by Williams and Parker [Will83] is still remarkably current in its enumeration of DFT techniques (it lacks Boundary-Scan of course), but many of the contexts have changed. For example, signature analysis [Nadi77] testing is now conducted on-chip, though it started as a board-level technique. This reflects the incredible increase in the density of Integrated Circuit (IC) components. In 1983, the 1149.1 Standard would have been largely impractical because the logic needed to implement it would have been a large fraction of an IC. Today, we are seeing ICs designed with significant amounts of on-chip testing circuitry, including 1149.1. Without DFT, a VLSI component might not be economical to produce in volume.