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Über dieses Buch

This book explains integrated circuit design for manufacturability (DfM) at the product level (packaging, applications) and applies engineering DfM principles to the latest standards of product development at 22 nm technology nodes. It is a valuable guide for layout designers, packaging engineers and quality engineers, covering DfM development from 1D to 4D, involving IC design flow setup, best practices, links to manufacturing and product definition, for process technologies down to 22 nm node, and product families including memories, logic, system-on-chip and system-in-package.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Preface

Abstract
What are the motivation and the approach for this book? Firstly, we intend to discuss the increasing number of key aspects of Integrated Circuit Design for Manufacturability in the early 2010’s. Because the speed of information in this area is critical for making money in IC manufacturing, DfM is a popular topic for conferences and journals, and a directional summary is usually welcome by the experts in the field.
Artur Balasinski

Chapter 2. Classic DfM: From 2D to 3D

Abstract
“Manufacturability” is the ability to make large numbers of identical products (IC devices), with substantially reproducible parameters in time and in space. Of course, these devices must perform a useful function, but that is ensured by their prototyping.
Artur Balasinski

Chapter 3. DfM at 28 nm and Beyond

Abstract
Introduction of more advanced technology nodes carries two key risks:
Artur Balasinski

Chapter 4. New DfM Domain: Stress Effects

Abstract
The mismatch of thermal properties among the IC component materials results in thermo-mechanical stress inside and around the devices [1–3]. It is tempting to divide the sources of such stress into the intentional and non-intentional ones or intrinsic and extrinsic. However, a better distinction would be whether we are able to take advantage of them in product implementation (intrinsic) or are they outside the device model space (extrinsic). When dividing them by the source of stress, one may identify the ones at die level, i.e., built into silicon, and the ones at package level, i.e., between the chip and its package. (Chip-Package Integration CPI). A DfM methodology for controlling stress, using design rules and material properties for both chip and package stack design, is required to span orders of magnitude of physical dimensions. It should not only comprehend the effects of mechanical stresses in electrical responses of the circuits, but also their reliability impact.
Artur Balasinski

Chapter 5. Closure and Future Work

Abstract
We have discussed three key trends in the IC Design for Manufacturability approaches of the early 2010’s, when key IC makers are moving along the Moore’s shrinkpath, passing the 28 nm technology node, on the way down to 22 nm and then, 15 nm.
Artur Balasinski

Backmatter

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