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2021 | Buch

Design for Testability, Debug and Reliability

Next Generation Measures Using Formal Techniques

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Über dieses Buch

This book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces.

Inhaltsverzeichnis

Frontmatter
Chapter 1. Introduction
Abstract
For several years, the design and fabrication of ICs no longer aim at producing devices, which fulfill one dedicated task. Instead, highly complex application scenarios are targeted, which require several heterogeneous functions to be jointly implemented on-chip at once. For this purpose, SoC designs have been successfully designed, which hold several nested modules, which inevitably lead to increasing complexity in the sense of transistor count. One important step towards this is the on-going reduction of the feature size of the used technology node, which implies that a single transistor is heavily shrunk.
Sebastian Huhn, Rolf Drechsler

Preliminaries and Previous Work

Frontmatter
Chapter 2. Integrated Circuits
Abstract
This chapter introduces the basic principles of the IC design and test. Furthermore, measurements are introduced, which ensure that the later IC design holds a high level of testability and reliability if this is required for the intended application. In particular, the abstract circuit model is presented in Sect. 2.1 and the principles of circuit test are described in Sect. 2.2. This includes the structural test in Sect. 2.2.1 and the functional test in Sect. 2.2.2.
Sebastian Huhn, Rolf Drechsler
Chapter 3. Formal Techniques
Abstract
This chapter introduces different formal techniques, which are invoked in Part II of this book, and, hence, are required for its comprehension. The described formal techniques include the SAT problem and the BMC. Furthermore, the concept of a FSM as well as a BDD are introduced as a symbolic model.
Sebastian Huhn, Rolf Drechsler

New Techniques for Test, Debug and Reliability

Frontmatter
Chapter 4. Embedded Compression Architecture for Test Access Ports
Abstract
Since recent years, the profile of functional requirements of ICs has been significantly changing. The ICs are no longer meant to be applied for dedicated functions only but they are designed to address several comprehensive tasks at once. This leads to complex SoC designs including several nested modules and, thus, to a large transistor count.
Sebastian Huhn, Rolf Drechsler
Chapter 5. Optimization SAT-Based Retargeting for Embedded Compression
Abstract
SoCs are now widely used in the semiconductor industry to fulfill the challenging functional requirements of nowadays application scenarios. This inevitably leads to higher test complexity since comprehensive test scenarios have to be considered for functional verification.
Sebastian Huhn, Rolf Drechsler
Chapter 6. Reconfigurable TAP Controllers with Embedded Compression
Abstract
The application of formal techniques within the retargeting procedure provides a powerful mechanism to determine the most beneficial—in the sense of TDV and TAT reduction—compressed test data D as well as a configuration C. This approach works well for small and mid-sized test data volume, though, the maximum size of test data that can be processed is strictly limited.
Sebastian Huhn, Rolf Drechsler
Chapter 7. Embedded Multichannel Test Compression for Low-Pin Count Test
Abstract
The latest accomplishments in the field of design and manufacturing of ICs enable entirely new application scenarios. For instance, the newest generation of electronic control units integrates a large number of sophisticated onboard ICs to implement advanced driver-assistance systems.
Sebastian Huhn, Rolf Drechsler
Chapter 8. Enhanced Reliability Using Formal Techniques
Abstract
Several breakthroughs in the field of the design, fabrication, and test of integrated circuits allowed for the implementation of highly complex ICs. These ICs fulfill several mission- or even safety-critical tasks at once while following a highly complex functional behavior.
Sebastian Huhn, Rolf Drechsler
Chapter 9. Conclusion and Outlook
Abstract
The integration of DFT measures is strictly required when designing state-of-the-art ICs to, among others, ensure that a good testability prevails in the resulting design. This testability allows performing high quality manufacturing tests, which give a certain level of confidence that no defects have occurred during the manufacturing process, which potentially tamper the correctness of the functional behavior.
Sebastian Huhn, Rolf Drechsler
Backmatter
Metadaten
Titel
Design for Testability, Debug and Reliability
verfasst von
Sebastian Huhn
Rolf Drechsler
Copyright-Jahr
2021
Electronic ISBN
978-3-030-69209-4
Print ISBN
978-3-030-69208-7
DOI
https://doi.org/10.1007/978-3-030-69209-4

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