Design of Area-Optimized Low-power Voltage Reference Circuits using a Modified Particle Swarm Optimization

The voltage reference circuit (VRC) is an important building block of many analog and mixed-signal system designs. In recent years, the requirement for smaller die area-based VRC has increased for the generation of constant reference voltages. In VRC design, the size of all the transistors has to satisfy all the design specifications. Traditionally integrated circuit (IC) designers use manual calculations or rely on the help of a simulator to design the VRC. Nowadays, designers prefer to use different evolutionary optimization techniques, such as particle swarm optimization (PSO), to design various analog circuits with multiple design constraints. PSO generally suffers from premature convergence and slow convergence speeds. In this work, these problems are addressed by designing VRCs using levy flight, power function, and Singer map-utilized particle swarm optimization (LPSPSO). The area along with other design parameters of VRCs, such as power dissipation, line sensitivity, and temperature coefficient, have been optimized to generate a constant reference voltage. The first VRC (VRC-I) and second VRC (VRC-II) were designed for targeted reference voltages of 550 mV and 255 mV, respectively. Both the VRCs were designed in Cadence with the transistor sizes obtained from the LPSPSO. The simulation results of VRC-I show a reference voltage of 550.9 mV with a 104-µm² die area and VRC-II resulted in a reference voltage of 254.8 mV with a 887.3-µm² die area. Both VRCs show improved figure of merit compared to their counterpart designs. The obtained results establish the effectiveness of LPSPSO in VRC design.